Intel 80960HA, 80960HD, 80960HT manual

Contents

Main 80960HA/HD/HT 32-Bit High-Performance Superscalar Processor Datasheet Product Features Page Contents Figures Page Tables Contents 6 Datasheet Revision History Contents Page 1.0About This Document 2.0Intel 80960Hx Processor 2.1The i960 Processor Family 2.2Key 80960Hx Features 2.2.1Execution Architecture 2.2.2Pipelined, Burst Bus Page 2.2.6Dual Programmable Timers 2.2.7Processor Self Test 80960HA/HD/HT Datasheet13 2.3Instruction Set Summary 3.0 Package Information 80960HA/HD/HT Datasheet15 3.1 Pin Descriptions 80960HA/HD/HT 16 Datasheet Table 7. 80960Hx Processor Family Pin Descriptions (Sheet 1 of 4) 80960HA/HD/HT Datasheet17 Table 7. 80960Hx Processor Family Pin Descriptions (Sheet 2 of 4) 80960HA/HD/HT 18 Datasheet Table 7. 80960Hx Processor Family Pin Descriptions (Sheet 3 of 4) 80960HA/HD/HT Datasheet19 Table 7. 80960Hx Processor Family Pin Descriptions (Sheet 4 of 4) 80960HA/HD/HT i XXXXXXXX SS 20 Datasheet 3.2 80960Hx Mechanical Data M 80960HA/HD/HT Datasheet21 Figure 3. 80960Hx 168-Pin PGA PinoutView from Bottom (Pins Facing Up) Package Lid 80960HA/HD/HT 22 Datasheet Table 8. 80960Hx 168-Pin PGA PinoutSignal Name Order (Sheet 1 of 2) 80960HA/HD/HT Datasheet23 Table 8. 80960Hx 168-Pin PGA PinoutSignal Name Order (Sheet 2 of 2) 80960HA/HD/HT 24 Datasheet Table 9. 80960Hx 168-Pin PGA PinoutPin Number Order (Sheet 1 of 2) 80960HA/HD/HT Datasheet25 Table 9. 80960Hx 168-Pin PGA PinoutPin Number Order (Sheet 2 of 2) 80960HA/HD/HT 26 Datasheet i960 80960HA/HD/HT Datasheet27 Table 10. 80960Hx PQ4 PinoutSignal Name Order (Sheet 1 of 2) 80960HA/HD/HT 28 Datasheet Table 10. 80960Hx PQ4 PinoutSignal Name Order (Sheet 2 of 2) 80960HA/HD/HT Datasheet29 Table 11. 80960Hx PQ4 PinoutPin Number Order (Sheet 1 of 2) 80960HA/HD/HT 30 Datasheet Table 11. 80960Hx PQ4 PinoutPin Number Order (Sheet 2 of 2) 3.3 Package Thermal Specifications 80960HA/HD/HT 32 Datasheet Table 12. Maximum TA at Various Airflows in C (PGA Package Only) Table 13. 80960Hx 168-Pin PGA Package Thermal Characteristics 80960HA/HD/HT Datasheet33 Table 14. Maximum TA at Various Airflows in C (PQ4 Package Only) Table 15. 80960Hx 208-Pin PQ4 Package Thermal Characteristics 3.4Heat Sink Adhesives 3.5PowerQuad4 Plastic Package 3.6 Stepping Register Information Page 3.7Sources for Accessories 4.0Electrical Specifications 4.1 Absolute Maximum Ratings 4.2Operating Conditions 4.3 Recommended Connections 4.4 VCC5 Pin Requirements (VDIFF) 4.5VCCPLL Pin Requirements 80960HA/HD/HT 40 Datasheet 4.6 D.C. Specifications Table 22. 80960Hx D.C. Characteristics (Sheet 1 of 2) 80960HA/HD/HT Datasheet41 Table 22. 80960Hx D.C. Characteristics (Sheet 2 of 2) 80960HA/HD/HT 42 Datasheet 4.7 A.C. Specifications Table 23. 80960Hx A.C. Characteristics (Sheet 1 of 2) 80960HA/HD/HT Datasheet43 Table 23. 80960Hx A.C. Characteristics (Sheet 2 of 2) 80960HA/HD/HT 44 Datasheet Table 24. A.C. Characteristics Notes Table 25. 80960Hx Boundary Scan Test Signal Timings 4.7.1 A.C. Test Conditions 80960HA/HD/HT 46 Datasheet 4.8 A.C. Timing Waveforms Figure 11. Output Delay Waveform Figure 9. CLKIN Waveform Figure 10. Output Delay Waveform 80960HA/HD/HT Datasheet47 Figure 12. Output Float Waveform Figure 14. NMI, XINT7:0 Input Setup and Hold Waveform Figure 13. Input Setup and Hold Waveform 80960HA/HD/HT 48 Datasheet Figure 15. Hold Acknowledge Timings Figure 16. Bus Backoff (BOFF) Timings 80960HA/HD/HT Datasheet49 Figure 17. TCK Waveform Figure 18. Input Setup and Hold Waveforms for TBSIS1 and TBSIH1 80960HA/HD/HT 50 Datasheet Figure 19. Output Delay and Output Float for TBSOV1 and TBSOF1 Figure 21. Input Setup and Hold Waveform for TBSIS2 and TBSIH2 Figure 20. Output Delay and Output Float Waveform for TBSOV2 and TBSOF2 80960HA/HD/HT Datasheet51 Figure 22. Rise and Fall Time Derating at 85 C and Minimum VCC Figure 23. ICC Active (Power Supply) vs. Frequency 80960HA/HD/HT 52 Datasheet Figure 24. ICC Active (Thermal) vs. Frequency Figure 25. Output Delay or Hold vs. Load Capacitance HA HT 80960HA/HD/HT Datasheet53 Figure 26. Output Delay vs. Temperature Figure 28. Output Delay vs. VCC Figure 27. Output Hold Times vs. Temperature 5.0 Bus Waveforms Page Page 80960HA/HD/HT Datasheet57 Figure 32. Non-Burst, Non-Pipelined Requests without Wait States 80960HA/HD/HT 58 Datasheet Figure 33. Non-Burst, Non-Pipelined Read Request with Wait States 80960HA/HD/HT Datasheet59 Figure 34. Non-Burst, Non-Pipelined Write Request with Wait States 80960HA/HD/HT 60 Datasheet Figure 35. Burst, Non-Pipelined Read Request without Wait States, 32-Bit Bus 80960HA/HD/HT Datasheet61 Figure 36. Burst, Non-Pipelined Read Request with Wait States, 32-Bit Bus 80960HA/HD/HT 62 Datasheet Figure 37. Burst, Non-Pipelined Write Request without Wait States, 32-Bit Bus 80960HA/HD/HT Datasheet63 Figure 38. Burst, Non-Pipelined Write Request with Wait States, 32-Bit Bus 80960HA/HD/HT 64 Datasheet Figure 39. Burst, Non-Pipelined Read Request with Wait States, 16-Bit Bus 80960HA/HD/HT Datasheet65 Figure 40. Burst, Non-Pipelined Read Request with Wait States, 8-Bit Bus 80960HA/HD/HT 66 Datasheet Figure 41. Non-Burst, Pipelined Read Request without Wait States, 32-Bit Bus 80960HA/HD/HT Datasheet67 Figure 42. Non-Burst, Pipelined Read Request with Wait States, 32-Bit Bus 80960HA/HD/HT 68 Datasheet Figure 43. Burst, Pipelined Read Request without Wait States, 32-Bit Bus 80960HA/HD/HT Datasheet69 Figure 44. Burst, Pipelined Read Request with Wait States, 32-Bit Bus 80960HA/HD/HT 70 Datasheet Figure 45. Burst, Pipelined Read Request with Wait States, 8-Bit Bus 80960HA/HD/HT Datasheet71 Figure 46. Burst, Pipelined Read Request with Wait States, 16-Bit Bus 80960HA/HD/HT 72 Datasheet Figure 47. Using External READY 80960HA/HD/HT Datasheet73 Figure 48. Terminating a Burst with BTERM Page Page 80960HA/HD/HT 76 Datasheet Figure 51. HOLD Functional Timing Page 80960HA/HD/HT 78 Datasheet Figure 54. A Summary of Aligned and Unaligned Transfers for 32-Bit Regions 80960HA/HD/HT Datasheet79 Figure 55. A Summary of Aligned and Unaligned Transfers for 32-Bit Regions (Continued) 04812162024 80960HA/HD/HT 80 Datasheet Figure 56. A Summary of Aligned and Unaligned Transfers for 16-Bit Bus 80960HA/HD/HT Datasheet81 Figure 57. A Summary of Aligned and Unaligned Transfers for 8-Bit Bus 80960HA/HD/HT 82 Datasheet Figure 58. Idle Bus Operation 80960HA/HD/HT Datasheet83 Figure 59. Bus States 80960HA/HD/HT 84 Datasheet 5.1 80960Hx Boundary Scan Chain Table 26. 80960Hx Boundary Scan Chain (Sheet 1 of 4) 80960HA/HD/HT Datasheet85 Table 26. 80960Hx Boundary Scan Chain (Sheet 2 of 4) 80960HA/HD/HT 86 Datasheet Table 26. 80960Hx Boundary Scan Chain (Sheet 3 of 4) 80960HA/HD/HT Datasheet87 Table 26. 80960Hx Boundary Scan Chain (Sheet 4 of 4) 5.2 Boundary Scan Description Language Example 80960HA/HD/HT Package Example (Sheet 2 of 8) Datasheet89 80960HA/HD/HT Package Example (Sheet 3 of 8) 90 Datasheet 80960HA/HD/HT Package Example (Sheet 4 of 8) Datasheet91 80960HA/HD/HT Package Example (Sheet 5 of 8) 92 Datasheet 80960HA/HD/HT Package Example (Sheet 6 of 8) Datasheet93 80960HA/HD/HT Package Example (Sheet 7 of 8) 94 Datasheet 80960HA/HD/HT Package Example (Sheet 8 of 8) Datasheet95 80960HA/HD/HT 96 Datasheet Package Example (Sheet 1 of 8) 80960HA/HD/HT Package Example (Sheet 2 of 8) Datasheet97 80960HA/HD/HT Package Example (Sheet 3 of 8) 98 Datasheet 80960HA/HD/HT Package Example (Sheet 4 of 8) Datasheet99 80960HA/HD/HT Package Example (Sheet 5 of 8) 100 Datasheet 80960HA/HD/HT Package Example (Sheet 6 of 8) Datasheet101 80960HA/HD/HT Package Example (Sheet 7 of 8) 102 Datasheet 80960HA/HD/HT Package Example (Sheet 8 of 8) Datasheet103