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Intel 80960HD, 80960HT, 80960HA manual Vccpll Pin Requirements, Sym Parameter Min Max Units

Models: 80960HT 80960HA 80960HD

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80960HA/HD/HT

Table 21. VDIFF Specification for Dual Power Supply Requirements (3.3 V, 5 V)

Sym	Parameter	Min	Max	Units	Notes

VDIFF	VCC5-VCC		2.25	V	VCC5 input should not exceed VCC by more than 2.25 V during
VDIFF	Difference		2.25	V	power-up and power-down, or during steady-state operation.

4.5VCCPLL Pin Requirements

When the voltage on the VCCPLL power supply pin exceeds the VCC pin voltage by 0.5 V at any time, including the power up and power down sequences, excessive currents may permanently damage on-chip electrostatic discharge (ESD) protection diodes. The damage may accumulate over multiple episodes.

Pragmatically, this problem only occurs when the VCCPLL and VCC pins are driven by separate power supplies or voltage regulators. Applications that use one power supply for VCCPLL and VCC are not typically at risk. Verify that your application does not allow the VCCPLL voltage to exceed VCC by 0.5 V.

The VCCPL low-pass filter recommended in the Developer’s Manual does not promote this problem.

Datasheet

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Intel 80960HD, 80960HT, 80960HA manual Vccpll Pin Requirements, Sym Parameter Min Max Units

Contents

80960HA/HD/HT 32-Bit High-Performance Superscalar Processor Datasheet Contents Contents Tables History DateDate Revision History 80960Hx AC Characteristics onThis page intentionally left blank Product Core Voltage Operating Frequency bus/core Hx Product DescriptionI960 Processor Family Key 80960Hx FeaturesOn-Chip Caches and Data RAM Bit When Set Fail Codes For Bist bit 7 =Remaining Fail Codes bit 7 = Data Movement Arithmetic Logical Bit / Bit Field / Byte Comparison Branch Call/Return FaultInstruction Set Summary Hx Instruction SetPackage/Name Device Core Speed Bus Speed Order # MHz HA/HD/HT Package Types and SpeedsSymbol Description Pin DescriptionsPin Description Nomenclature Name Type Description Hx Processor Family Pin Descriptions Sheet 1SUP Hx Processor Family Pin Descriptions Sheet 2Hold Hx Processor Family Pin Descriptions Sheet 3Clkin Hx Processor Family Pin Descriptions Sheet 480960Hx Mechanical Data Hx 168-Pin PGA Pinout- View from Top Pins Facing DownHx 168-Pin PGA Pinout- View from Bottom Pins Facing Up Hx 168-Pin PGA Pinout- Signal Name Order Sheet 1 Signal NamePin Hx 168-Pin PGA Pinout- Signal Name Order Sheet 2 Hx 168-Pin PGA Pinout- Pin Number Order Sheet 1 Hx 168-Pin PGA Pinout- Pin Number Order Sheet 2 I960 Hx PQ4 Pinout- Signal Name Order Sheet 1 Hx PQ4 Pinout- Signal Name Order Sheet 2 Pin Number Order Sheet 1 Pin Number Order Sheet 2 Equation 1. Calculation of Ambient Temperature TA Package Thermal Specifications600 Hx 168-Pin PGA Package Thermal CharacteristicsMaximum TA at Various Airflows in C PGA Package Only Airflow-ft/min m/sec400 Hx 208-Pin PQ4 Package Thermal CharacteristicsMaximum TA at Various Airflows in C PQ4 Package Only Thermal Resistance C/Watt Airflow ft./min m/sec ParameterPowerQuad4 Plastic Package Heat Sink AdhesivesStepping Register Information Fields of 80960Hx Device ID Hx Device ID Model TypesDevice ID Version Numbers for Different Steppings Sockets Sources for AccessoriesOperating Conditions Absolute Maximum RatingsOperating Conditions Absolute Maximum RatingsVCC5 Pin Requirements Vdiff Recommended ConnectionsSym Parameter Min Max Units Vccpll Pin RequirementsD.C.Specifications Hx D.C. Characteristics Sheet 1Symbol Parameter Min Typ Max Units Sheet 2 Hx D.C. CharacteristicsSynchronous Outputs 1, 2, 3 A.C. SpecificationsHx A.C. Characteristics Sheet 1 Symbol Parameter Min Max Units Input Clock 1Hx A.C. Characteristics Sheet 2 Relative Output Timings 1, 2, 3, 6Relative Input Timings 1, 7 Hx Boundary Scan Test Signal Timings C. Characteristics Notes1 A.C. Test Conditions Clkin Waveform A.C. Timing WaveformsOutput Float Waveform Hold Acknowledge Timings TCK Waveform Output Delay and Output Float for TBSOV1 and TBSOF1 Rise and Fall Time Derating at 85 C and Minimum VCC ICC Active Thermal vs. Frequency Output Delay vs. Temperature Bus ∼ ∼ Reset Once Once ModeNon-Burst, Non-Pipelined Requests without Wait States Non-Burst, Non-Pipelined Read Request with Wait States Non-Burst, Non-Pipelined Write Request with Wait States BE30, Lock Blast DT/R DEN A314, SUP CT30, D/C Valid Lock Blast DT/R DEN A314, SUP Valid CT30, D/C Lock Blast DT/R DEN Wait Blast DT/R DEN Pchk Wait Blast BE30, Lock Burst, Pipelined Read Request with Wait States, 32-Bit Bus Burst, Pipelined Read Request with Wait States, 8-Bit Bus Burst, Pipelined Read Request with Wait States, 16-Bit Bus Using External Ready Terminating a Burst with Bterm Breq and Bstall Operation Clkin ADS Blast Ready Hold Functional Timing Lock Delays Holda Timing Byte Offset Word Offset 80960HA/HD/HT Summary of Aligned and Unaligned Transfers for 16-Bit Bus Summary of Aligned and Unaligned Transfers for 8-Bit Bus Idle Bus Operation Bus States 80960Hx Boundary Scan Chain Hx Boundary Scan Chain Sheet 1Boundary Scan Cell Cell Type Comment Lockbar Hx Boundary Scan Chain Sheet 2Nmibar Hx Boundary Scan Chain Sheet 3Pchk Hx Boundary Scan Chain Sheet 4Boundary Scan Description Language Example Adsbar Supbar E03, C02, D02, C01, E02, D01, F02, E01, F01 Bypass Input BC1 BEBAR3 XINTBAR7 80960HA/HD/HT Adsbar Adsbar Bebar Oncebar Pchkbar 100 Datasheet 101 102 Datasheet 103 104