Contents

Revision History

Date

Revision

 

 

History

 

 

 

 

 

Formatted the datasheet in a new template.

 

 

In “32-Bit Parallel Architecture” on page 1:

 

 

• Removed operating frequency of 16/32 (bus/core) from 80960HD.

 

 

• Removed operating frequency of 20/60 (bus/core) from 80960HT.

 

 

In Table 5 “80960HA/HD/HT Package Types and Speeds” on page 14:

 

 

• Removed core speed of 32 MHz and bus speed of 16 MHz, and order

 

 

 

number A80960HD32-S-L2GG from the 168L PGA package, 80960HD

September 2002

008

 

device.

 

 

• Removed core speed of 60 MHz and bus speed of 20 MHz, and order

 

 

 

number A80960HT60 from the 168L PGA package, 80960HT device.

 

 

• Removed core speed of 32 MHz and bus speed of 16 MHz, and order

 

 

 

number FC80960HD32-S-L2GL from the 208L PQFP package,

 

 

 

80960HD device.

 

 

• Removed core speed of 60 MHz and bus speed of 20 MHz, and order

 

 

 

number FC80960HT60-S-L2G2 from the 208L PQFP package,

 

 

 

80960HT device.

 

 

 

 

 

In “32-Bit Parallel Architecture” on page 1:

 

 

• Revised 1.2 Gbyte Internal Bandwidth (75 MHz) to 1.28 Gbyte Internal

 

 

 

Bandwidth (80 MHz).

 

 

In Section 3.0, “Package Information” on page 14:

 

 

• Added paragraph two and Table 5 “80960HA/HD/HT Package Types

 

 

 

and Speeds” on page 14.

 

 

In Table 7 “80960Hx Processor Family Pin Descriptions” on page 16:

 

 

• Corrected minor typeset and spacing errors.

 

 

•

BREQ; Revised description.

 

 

 

 

 

•

ONCE;

last sentence, changed ‘low’ to ‘high’.

 

 

• TDI and TMS; removed last sentence stating, “Pull this pin low when

 

 

 

not in use.”

 

 

In Figure 2 “80960Hx 168-Pin PGA Pinout— View from Top (Pins Facing

 

 

Down)” on page 20:

July 1998

007

•

Added insert package marking diagram.

 

 

In Figure 4 “80960Hx 208-Pin PQ4 Pinout” on page 26:

 

 

• Added insert package marking diagram.

 

 

In Table 10 “80960Hx PQ4 Pinout— Signal Name Order” on page 27:

•Corrected TDO (‘O’ was zero) and revised alphabetical ordering. In Table 11 “80960Hx PQ4 Pinout— Pin Number Order” on page 29:

•Corrected TDO (‘O’ was zero) and revised alphabetical ordering. In Section 4.1, “Absolute Maximum Ratings” on page 37:

•Revised VCC to VCC5 for Voltage on Other Pins with respect to VSS. In Section 4.5, “VCCPLL Pin Requirements” on page 39:

•Added section.

In Table 22 “80960Hx DC Characteristics” on page 40:

•Added footnote (1) to ILO notes column for TDO pin.

•Added footnote (10) to CIN, COUT and CI/O pin.

6

Datasheet

Page 5 Page 7
Page 6
Image 6
Intel 80960HD, 80960HT, 80960HA manual Date, History
Page 5 Page 7

80960HT, 80960HA, 80960HD specifications

The Intel 80960 family of microprocessors, introduced in the late 1980s, marked a significant evolution in the landscape of embedded systems and high-performance computing. The series included notable members such as the 80960HD, 80960HA, and 80960HT, each offering distinct features, technologies, and characteristics tailored for specific applications.

The Intel 80960HD was primarily designed for high-performance applications, such as real-time processing and advanced embedded control systems. With a robust architecture, the 80960HD featured a 32-bit data bus and a 32-bit address bus, enabling it to access a larger memory space and providing superior performance for computational tasks. It included a sophisticated instruction set that facilitated efficient execution, particularly for computationally intensive tasks. The internal architecture also supported pipelining, allowing multiple instructions to be processed simultaneously, thus enhancing throughput.

The 80960HA variant was tailored for high-availability applications, making it ideal for embedded systems where reliability is paramount. This model incorporated features that emphasized fault tolerance and stability, ensuring that systems relying on it could maintain operational integrity even in the event of component failures. The 80960HA showcased enhanced error detection and correction capabilities, which contributed to its reputation as a dependable choice for mission-critical applications.

On the other hand, the 80960HT was designed to meet the needs of high-performance telecommunications and networking applications. Recognized for its ability to handle multiple tasks concurrently, the 80960HT included advanced features such as built-in support for multitasking and real-time processing. This made it an excellent fit for applications that demanded rapid data handling and processing, such as routers and switches in networking environments. Its architecture allowed for efficient context switching, ensuring that multiple processes could execute seamlessly.

All three variants utilized the same family architecture, enabling easy integration and compatibility across different applications. They also supported various memory management techniques, such as virtual memory and caching, enhancing their performance in diverse operating conditions. With their combination of high processing power, reliability, and flexibility, the Intel 80960 family of microprocessors played a crucial role in advancing embedded computing technologies, paving the way for modern-day processors and systems. The 80960 series remains a noteworthy chapter in the evolution of microprocessor design, reflecting the growing demands of the computing landscape during its time.
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