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Intel 80960HT, 80960HD, 80960HA manual ∼ ∼

Models: 80960HT 80960HA 80960HD

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Datasheet

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CLKIN				Figure 30. Warm Reset
CLKIN		∼ ∼	∼ ∼	Waveform
W/R, BREQ, FAIL,		∼ ∼	∼ ∼	Waveform
ADS,
LOCK, WAIT,
DEN, BLAST,
BSTALL
DT/R
		∼	∼
SUP,			∼
A31:2,		∼
D/C, BE3:0			∼
D31:0,
DP3:0		∼	∼
DP3:0
		∼	∼
STEST		Valid
	Maximum RESET Low to RESET State	∼	∼
	Maximum RESET Low to RESET State	Tsetup	Thold
	16 CLKIN Periods	Tsetup	Thold
	16 CLKIN Periods	1 CLKIN	1 CLKIN
		1 CLKIN	1 CLKIN
			∼
RESET
		∼
			RESET High to First Bus Activity,
			HA=67, HD=34, HT=23
			CLKIN Periods
	Minimum RESET Low Time
	16 CLKIN Periods

80960HA/HD/HT

Image 55

Intel 80960HT, 80960HD, 80960HA manual ∼ ∼

Contents

80960HA/HD/HT 32-Bit High-Performance Superscalar Processor Datasheet Contents Contents Tables History DateDate Revision History 80960Hx AC Characteristics onThis page intentionally left blank Product Core Voltage Operating Frequency bus/core Hx Product DescriptionI960 Processor Family Key 80960Hx FeaturesOn-Chip Caches and Data RAM Fail Codes For Bist bit 7 = Bit When SetRemaining Fail Codes bit 7 = Data Movement Arithmetic Logical Bit / Bit Field / Byte Comparison Branch Call/Return FaultInstruction Set Summary Hx Instruction SetPackage/Name Device Core Speed Bus Speed Order # MHz HA/HD/HT Package Types and SpeedsPin Descriptions Symbol DescriptionPin Description Nomenclature Name Type Description Hx Processor Family Pin Descriptions Sheet 1SUP Hx Processor Family Pin Descriptions Sheet 2Hold Hx Processor Family Pin Descriptions Sheet 3Clkin Hx Processor Family Pin Descriptions Sheet 480960Hx Mechanical Data Hx 168-Pin PGA Pinout- View from Top Pins Facing DownHx 168-Pin PGA Pinout- View from Bottom Pins Facing Up Signal Name Hx 168-Pin PGA Pinout- Signal Name Order Sheet 1Pin Hx 168-Pin PGA Pinout- Signal Name Order Sheet 2 Hx 168-Pin PGA Pinout- Pin Number Order Sheet 1 Hx 168-Pin PGA Pinout- Pin Number Order Sheet 2 I960 Hx PQ4 Pinout- Signal Name Order Sheet 1 Hx PQ4 Pinout- Signal Name Order Sheet 2 Pin Number Order Sheet 1 Pin Number Order Sheet 2 Equation 1. Calculation of Ambient Temperature TA Package Thermal Specifications600 Hx 168-Pin PGA Package Thermal CharacteristicsMaximum TA at Various Airflows in C PGA Package Only Airflow-ft/min m/sec400 Hx 208-Pin PQ4 Package Thermal CharacteristicsMaximum TA at Various Airflows in C PQ4 Package Only Thermal Resistance C/Watt Airflow ft./min m/sec ParameterHeat Sink Adhesives PowerQuad4 Plastic PackageStepping Register Information Hx Device ID Model Types Fields of 80960Hx Device IDDevice ID Version Numbers for Different Steppings Sockets Sources for AccessoriesOperating Conditions Absolute Maximum RatingsOperating Conditions Absolute Maximum RatingsVCC5 Pin Requirements Vdiff Recommended ConnectionsSym Parameter Min Max Units Vccpll Pin RequirementsHx D.C. Characteristics Sheet 1 D.C.SpecificationsSymbol Parameter Min Typ Max Units Sheet 2 Hx D.C. CharacteristicsSynchronous Outputs 1, 2, 3 A.C. SpecificationsHx A.C. Characteristics Sheet 1 Symbol Parameter Min Max Units Input Clock 1Relative Output Timings 1, 2, 3, 6 Hx A.C. Characteristics Sheet 2Relative Input Timings 1, 7 Hx Boundary Scan Test Signal Timings C. Characteristics Notes1 A.C. Test Conditions Clkin Waveform A.C. Timing WaveformsOutput Float Waveform Hold Acknowledge Timings TCK Waveform Output Delay and Output Float for TBSOV1 and TBSOF1 Rise and Fall Time Derating at 85 C and Minimum VCC ICC Active Thermal vs. Frequency Output Delay vs. Temperature Bus ∼ ∼ Reset Once Once ModeNon-Burst, Non-Pipelined Requests without Wait States Non-Burst, Non-Pipelined Read Request with Wait States Non-Burst, Non-Pipelined Write Request with Wait States BE30, Lock Blast DT/R DEN A314, SUP CT30, D/C Valid Lock Blast DT/R DEN A314, SUP Valid CT30, D/C Lock Blast DT/R DEN Wait Blast DT/R DEN Pchk Wait Blast BE30, Lock Burst, Pipelined Read Request with Wait States, 32-Bit Bus Burst, Pipelined Read Request with Wait States, 8-Bit Bus Burst, Pipelined Read Request with Wait States, 16-Bit Bus Using External Ready Terminating a Burst with Bterm Breq and Bstall Operation Clkin ADS Blast Ready Hold Functional Timing Lock Delays Holda Timing Byte Offset Word Offset 80960HA/HD/HT Summary of Aligned and Unaligned Transfers for 16-Bit Bus Summary of Aligned and Unaligned Transfers for 8-Bit Bus Idle Bus Operation Bus States Hx Boundary Scan Chain Sheet 1 80960Hx Boundary Scan ChainBoundary Scan Cell Cell Type Comment Lockbar Hx Boundary Scan Chain Sheet 2Nmibar Hx Boundary Scan Chain Sheet 3Pchk Hx Boundary Scan Chain Sheet 4Boundary Scan Description Language Example Adsbar Supbar E03, C02, D02, C01, E02, D01, F02, E01, F01 Bypass Input BC1 BEBAR3 XINTBAR7 80960HA/HD/HT Adsbar Adsbar Bebar Oncebar Pchkbar 100 Datasheet 101 102 Datasheet 103 104