Intel 80960HT, 80960HD, 80960HA manual Burst, Pipelined Read Request with Wait States, 8-Bit Bus

80960HA/HD/HT

Figure 45. Burst, Pipelined Read Request with Wait States, 8-Bit Bus

PMCON

External

Pipe-

Bus

Odd

Parity

NRAD

Function

Ready

Burst

NXDA

NWDD

NWAD

NRDD

Lining

Width

Parity

Enable

Control

Bit

29

28

24

23-22

21

20

19-16

15-14

12-8

7-6

4-0

Value

X

Enabled

ON

8-Bit

X

Enabled

X

X

X

1

2

x

1

1

00

x

1

xxxx

xx

xxxxx

01

00010

NOTE: Bits 31-30, 27-25, 13, and 5 are reserved.

D’ 2

1 A

2

1

D

1

D

1

D

1

A’

2

1

D

CLKIN

ADS

A31:4, SUP,

Valid

In-

CT3:0, D/C,

Valid

valid

LOCK

W/R

In-

valid

A3:2

A3:2 = 00, 01, 10, or 11

Valid

In-

valid

BE1/A1,

A1:0 = 00

A1:0 = 01

A1:0 = 10

A1:0 = 11

Valid

In-

BE0/A0

valid

D31:0,

D7:0

D7:0

D7:0

D7:0

D7:0

DP3:0

Byte 0

Byte 1

Byte 2

Byte 3

D’

WAIT

BLAST

DT/R

DEN

PCHK

1. Non-pipelined request concludes, pipelined reads begin

2. Pipelined reads conclude, non-pipelined requests begin

70 Datasheet