Intel 80960HA, 80960HD, 80960HT manual BE30, Lock

80960HA/HD/HT

Figure 43. Burst, Pipelined Read Request without Wait States, 32-Bit Bus

PMCON

External

Pipe-

Bus

Odd

Parity

NRAD

Function

Ready

Burst

NXDA

NWDD

NWAD

NRDD

Lining

Width

Parity

Enable

Control

Bit

29

28

24

23-22

21

20

19-16

15-14

12-8

7-6

4-0

Value

X

Enabled

ON

32-Bit

X

Enabled

X

X

X

0

0

x

1

1

10

x

1

xxxx

xx

xxxxx

00

00000

NOTE: Bits 31-30, 27-25, 13, and 5 are reserved.

1 A

D

D

D

A’

D’

D’ 2

D

CLKIN

ADS

A31:4, SUP,

CT3:0, D/C,

Valid

Valid

In-

BE3:0, LOCK

Valid

W/R

A3:2

00

01

10

11

Valid

Valid

In-

Valid

D31:0,

IN

IN

IN

IN

IN

IN

DP3:0

D

D

D

D

D

D

WAIT

BLAST

DT/R

DEN

PCHK

1. Non-pipelined request concludes, pipelined reads begin

2. Pipelined reads conclude, non-pipelined requests begin

68

Datasheet