Intel 80960HT, 80960HD manual Hx Processor Family Pin Descriptions Sheet 1, Name Type Description

80960HA/HD/HT

Table 7. 80960Hx Processor Family Pin Descriptions (Sheet 1 of 4)

Name	Type	Description
	O	ADDRESS BUS carries the upper 30 bits of the physical address. A31 is the most
		significant address bit and A2 is the least significant. During a bus access, A31:2
A31:2	H(Z)
		identify all external addresses to word (4-byte) boundaries. The byte enable
	B(Z)
		signals indicate the selected byte in each word. During burst accesses, A3 and
	R(Z)
		A2 increment to indicate successive addresses.
	I/O	DATA BUS carries 32, 16, or 8-bit data quantities depending on bus width
	S(L)
D31:0		configuration. The least significant bit of the data is carried on D0 and the most
	H(Z)
		significant on D31. The lower eight data lines (D7:0) are used when the bus is
	B(Z)
		configured for 8-bit data. When configured for 16-bit data, D15:0 are used.
	R(Z)
		DATA PARITY carries parity information for the data bus. Each parity bit is
		assigned a group of eight data bus pins as follows:
	I/O	DP3 generates/checks parity for D31:24
DP3:0	S(L)	DP2 generates/checks parity for D23:16
	H(Z)	DP1 generates/checks parity for D15:8
	B(Z)	DP0 generates/checks parity for D7:0
	R(Z)	Parity information is generated for a processor write cycle and is checked for a
		processor read cycle. Parity checking and polarity are programmable. Parity
		generation/checking is only performed for the size of the data accessed.
	O
	H(Q)	PARITY CHECK indicates the result of a parity check operation. An asserted
PCHK
	B(Q)	PCHK indicates that the previous bus read access resulted in a parity check error.
	R(1)
		BYTE ENABLES select which of the four bytes addressed by A31:2 are active
		during a bus access. Byte enable encoding is dependent on the bus width of the
		memory region accessed:
		32-bit bus:
		BE3 enables D31:24
		BE2 enables D23:16
	O	BE1 enables D15:8
		BE0 enables D7:0
	H(Z)	16-bit bus:
BE3:0
	B(Z)	BE3 becomes Byte High Enable (enables D15:8)
	R(1)	BE2 is not used (state is undefined)
		BE1 becomes Address Bit 1 (A1)
		BE0 becomes Byte Low Enable (enables D7:0)
		8-bit bus:
		BE3 is not used (state is undefined)
		BE2 is not used (state is undefined)
		BE1 Address Bit 1 (A1)
		BE0 Address Bit 0 (A0)
	O	WRITE/READ is low for read accesses and high for write accesses.
		W/R becomes valid during the address phase of a bus cycle and remains valid
	H(Z)	until the end of the cycle for non-pipelined accesses. For pipelined accesses, W/
W/R
		R changes state when the next address is presented.
	B(Z)
		0= Read
	R(0)
		1= Write
	O	DATA/CODE indicates that a bus access is a data access or an instruction
	H(Z)	access. D/C has the same timing as W/R.
D/C
		0 = Code
	B(Z)
	R(0)	1 = Data

16 Datasheet