56
Datasheet
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| CLKIN may neither float nor remain idle. | |
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| It must continue to run. | |
CLKIN |
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VCC, VCC5 |
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ADS, BE3:0, A31:2, |
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D31:0, LOCK, WAIT, |
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BLAST,W/R, D/C, DEN, |
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DT/R, HOLDA, |
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BLAST, FAIL, SUP,BREQ, | ∼ | ∼ |
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CT3:0, BSTALL, DP3:0, |
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PCHK |
| ONCE mode is entered within 1 CLKIN |
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| period after ONCE becomes low while |
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| RESET is low. |
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RESET |
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ONCE |
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CLKIN and VCC Stable and RESET low and ONCE low to
RESET high, minimum 10,000 CLKIN Periods.
NOTES:
1.ONCE mode may be entered prior to the rising edge of RESET: ONCE input is not latched until the rising edge of RESET.
2.The ONCE input may be removed after the processor enters ONCE mode.
Figure 31. Entering | 80960HA/HD/HT |
ONCE Mode |
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