80960HA/HD/HT
Table 7. 80960Hx Processor Family Pin Descriptions (Sheet 4 of 4)
|
| Name | Type |
| Description |
| |||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
| |||||||
|
|
|
|
|
|
|
|
|
|
| CLOCK INPUT provides the time base for the 80960Hx. All internal circuitry is |
| |||||||
|
|
|
|
|
|
|
|
|
|
| synchronized to CLKIN. All input and output timings are specified relative to |
| |||||||
| CLKIN | I |
| CLKIN. |
| ||||||||||||||
|
| For the 80960HD, the 2x internal clock is derived by multiplying the CLKIN |
| ||||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
| ||||||||
|
|
|
|
|
|
|
|
|
|
| frequency by two. For the 80960HT, the 3x internal clock is derived by multiplying |
| |||||||
|
|
|
|
|
|
|
|
|
|
| the CLKIN frequency by three. |
| |||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| I |
| RESET forces the device into reset. | RESET | causes all external and internal |
| |||||
| RESET |
|
|
|
|
|
|
|
|
|
|
| |||||||
| signals to return to their reset state (when defined). The rising edge of RESET |
| |||||||||||||||||
| A(L) |
|
| ||||||||||||||||
|
|
|
|
|
|
|
|
|
| starts the processor boot sequence. |
| ||||||||
|
|
|
|
|
|
|
|
|
|
|
| ||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
| ||||||
|
|
|
|
|
|
|
|
| I |
| SELF TEST, when asserted during the rising edge of |
| causes the |
| |||||
| STEST | RESET, |
| ||||||||||||||||
| S(L) |
| processor to execute its built in |
| |||||||||||||||
|
|
|
|
|
|
|
|
|
|
| |||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
| ||||||
|
|
|
|
|
|
|
|
| O |
| FAIL indicates a failure of the processor’s |
| |||||||
|
|
|
|
|
|
|
|
|
| initialization. FAIL is asserted immediately out of reset and toggles during |
| ||||||||
|
|
|
|
|
|
|
|
| H(Q) |
|
| ||||||||
|
|
|
| FAIL |
| to indicate the status of individual tests. When |
| ||||||||||||
|
|
|
| B(Q) |
|
| |||||||||||||
|
|
|
|
|
|
|
|
|
| asserted and the processor branches to the user’s initialization code. When self- |
| ||||||||
|
|
|
|
|
|
|
|
| R(0) |
|
| ||||||||
|
|
|
|
|
|
|
|
|
| test fails, the FAIL pin asserts and the processor ceases execution. |
| ||||||||
|
|
|
|
|
|
|
|
|
|
|
| ||||||||
|
|
|
|
|
|
|
|
|
|
|
|
| |||||||
|
|
|
|
|
|
|
|
|
|
|
| ||||||||
|
|
|
|
|
|
|
|
| I |
| When it is asserted low at the end of reset, the processor enters ONCE mode. In |
| |||||||
|
| ONCE |
| ONCE mode, the processor stops all clocks and floats all output pins except the |
| ||||||||||||||
|
|
|
|
|
|
|
|
|
|
| TDO pin. ONCE uses an internal |
| |||||||
|
|
|
|
|
|
|
|
|
|
| “80960Hx DC Characteristics” on page 40. Pull this pin high when not in use. |
| |||||||
|
|
|
|
|
|
|
|
|
|
|
|
| |||||||
|
|
|
| TCK | I |
| TEST CLOCK provides the clocking function for IEEE 1149.1 Boundary Scan |
| |||||||||||
|
|
|
|
| testing. |
| |||||||||||||
|
|
|
|
|
|
|
|
|
|
|
| ||||||||
|
|
|
|
|
|
|
|
|
|
|
|
| |||||||
|
|
|
| TDI | I |
| TEST DATA INPUT is the serial input pin for IEEE 1149.1 Boundary Scan testing. |
| |||||||||||
|
|
|
|
| TDI uses an internal |
| |||||||||||||
|
|
|
|
|
|
|
|
|
|
| Characteristics” on page 40. |
| |||||||
|
|
|
|
|
|
|
|
|
|
|
|
| |||||||
|
|
|
| TDO | O |
| TEST DATA OUTPUT is the serial output pin for IEEE 1149.1 Boundary Scan |
| |||||||||||
|
|
|
|
| testing. ONCE does not disable this pin. |
| |||||||||||||
|
|
|
|
|
|
|
|
|
|
|
| ||||||||
|
|
|
|
|
|
|
|
|
|
|
|
| |||||||
|
|
|
|
|
|
|
|
|
|
| TEST RESET asynchronously resets the Test Access Port (TAP) controller. |
|
|
| |||||
|
|
|
|
|
|
|
|
|
|
| TRST |
| |||||||
|
|
|
|
|
|
|
|
| I |
| must be held low at least 10,000 clock cycles after |
| |||||||
|
|
| TRST |
| provide TRST with a separate |
| |||||||||||||
|
|
|
|
|
|
|
|
|
|
|
| ||||||||
|
|
|
|
|
|
|
|
|
|
| page 40. Pull this pin low when not in use. |
| |||||||
|
|
|
|
|
|
|
|
|
|
|
|
| |||||||
|
|
|
|
|
|
|
|
|
|
| TEST MODE SELECT is sampled at the rising edge of TCK. TCK controls the |
| |||||||
|
|
|
| TMS | I |
| sequence of TAP controller state changes for IEEE 1149.1 Boundary Scan |
| |||||||||||
|
|
|
|
| testing. TMS uses an internal |
| |||||||||||||
|
|
|
|
|
|
|
|
|
|
|
| ||||||||
|
|
|
|
|
|
|
|
|
|
| “80960Hx DC Characteristics” on page 40. |
| |||||||
|
|
|
|
|
|
|
|
|
|
|
|
| |||||||
|
| VCC5 | I |
| 5 V REFERENCE VOLTAGE input is the reference voltage for the 5 |
| |||||||||||||
|
|
| buffers. Connect this signal to +5 V for use with inputs which exceed 3.3 V. When |
| |||||||||||||||
|
|
|
|
|
|
|
|
|
|
| all inputs are from 3.3 V components, connect this signal to 3.3 V. |
| |||||||
|
|
|
|
| |||||||||||||||
VCCPLL | I |
| PLL VOLTAGE is the +3.3 VDC analog input for the PLL. |
| |||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
| |||||||
|
|
|
|
|
|
|
|
|
|
| VOLTAGE DETECT signal allows external system logic to distinguish between a |
| |||||||
|
|
|
|
|
|
|
|
|
|
| 5 V 80960Cx processor and the 3.3 V 80960Hx processor. This signal is active |
| |||||||
VOLDET | O |
| low for a 3.3 V 80960Hx (it is high impedance for 5 V 80960Cx). This pin is |
| |||||||||||||||
| available only on the PGA version. |
| |||||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
| ||||||||
|
|
|
|
|
|
|
|
|
|
| 0 = 80960Hx |
| |||||||
|
|
|
|
|
|
|
|
|
|
| 1 = 80960Cx |
| |||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Datasheet | 19 |