Intel 80960HA, 80960HD, 80960HT manual Non-Burst, Non-Pipelined Write Request with Wait States

80960HA/HD/HT

Figure 34. Non-Burst, Non-Pipelined Write Request with Wait States

PMCON	External
Function			Pipe-	Bus	Odd	Parity					NRAD
	Ready	Burst					NXDA	NWDD	NWAD	NRDD
			Lining	Width	Parity	Enable
	Control
Bit	29	28	24	23-22	21	20	19-16	15-14	12-8	7-6	4-0
Value	Disabled Disabled		OFF	X	X	Enabled	1	X	3	X	X
	0	0	0	xx	x	1	0001	xxxxx	00011	xx	xxxxx
	NOTE: Bits 31-30, 27-25, 13, and 5 are reserved.
		A		3	2	1		D	1		A
CLKIN
ADS
A31:2,						Valid
BE3:0
W/R
BLAST
DT/R
DEN
D/C, SUP,						Valid
LOCK, CT3:0
WAIT
D31:0,							Out
DP3:0
PCHK
Datasheet											59