Intel 80960HA, 80960HD, 80960HT manual Bus States

80960HA/HD/HT

Figure 59. Bus States

Tb

BOFF

BOFF

!BOFF

Ta

!RESET and !HOLD and

REQUEST

BOFF

!BOFF and READY and !BLAST or

!BOFF and BTERM and !BLAST or !BOFF and

!HOLD and BLAST and REQUEST and NXDA = 0

!BOFF and READ and Nrad = 0 or !BOFF and WRITE and Nwad = 0

WdCNT > 1

Tdw3

WdCNT = 1

READ and Nrdd > 0 or

WRITE and Nwdd > 0

Td1 !BOFF and READ and Nrdd = 0

and !BLAST or !BOFF and

WRITE and Nwdd = 0 and !BLAST or

READY!

READ and Nrad > 0 or

WRITE and Nwad > 0!BOFF and BLAST and Nxda > 0

Taw2	W CNT = 1
	a

WaCNT > 1

!HOLD and WxCNT=1

and REQUEST

To

			WxCNT=1 and
	RESET and
		!HOLD and WxCNT=1	HOLD
	!ONCE
ONCE and		and !REQUEST
		HOLD
RESET

Ti

HOLD

Th

!HOLD

RESET

Trw4 WxCNT > 1

!BOFF and !HOLD and

BLAST andNxda = 0 and !REQUEST

!BOFF and

HOLD and BLAST and Nxda= 0

KEY:

To = ONCE

Ti = IDLE

Th = HOLD

Ta = ADDRESS Td = DATA

Tb = BOFF’ed

Taw= address to data wait Tdw= data to data wait Tdw= data to address wait

REQUEST= One or more requests in the bus queue. READ= The current access is a read.

WRITE= The current access is a write.

NOTES:

1.When the PMCON for the region has External Ready Control enabled, wait states are inserted as long as READY and BTERM are de-asserted. When Read Pipelining is enabled, the Ta state of the subsequent read access is concurrent with the last data cycle of the access. Because External Ready Control is disabled for Read Pipelining, the address cycle occurs during BLAST.

2.WaCNT is decremented during Taw.

3.WdCNT is decremented during Tdw.

4.WxCNT is decremented during Trw.

Datasheet 83