Intel 80960HA, 80960HD, 80960HT manual Hx Processor Family Pin Descriptions Sheet 2, Sup

80960HA/HD/HT

Table 7. 80960Hx Processor Family Pin Descriptions (Sheet 2 of 4)

Name

Type

Description

O

SUPERVISOR ACCESS indicates whether the current bus access originates

from a request issued while in supervisor mode or user mode. SUP may be used

H(Z)

by the memory subsystem to isolate supervisor code and data structures from

SUP

non-supervisor access.

B(Z)

R(1)

0 = Supervisor Mode

1 = User Mode

O

H(Z)

ADDRESS STROBE indicates a valid address and the start of a new bus access.

ADS

B(Z)

ADS is asserted for the first clock of a bus access.

R(1)

READY, when enabled for a memory region, is asserted by the memory

subsystem to indicate the completion of a data transfer.

READY

is used to

indicate that read data on the bus is valid, or that a write transfer has completed.

I

READY works in conjunction with the internal wait state generator to

READY

S(L)

accommodate various memory speeds. READY is sampled after any

programmed wait states:

During each data cycle of a burst access

During the data cycle of a non-burst access

I

BURST TERMINATE, when enabled for a memory region, is asserted by the

memory subsystem to terminate a burst access in progress. When BTERM is

BTERM

S(L)

asserted, the current burst access is terminated and another address cycle

occurs.

O

WAIT indicates the status of the internal wait-state generator. WAIT is asserted

H(Z)

WAIT

when the internal wait state generator generates NWAD, NRAD, NWDD and NRDD

B(Z)

wait states. WAIT may be used to derive a write data strobe.

R(1)

BURST LAST indicates the last transfer in a bus access.

is asserted in

O

BLAST

the last data transfer of burst and non-burst accesses after the internal wait-state

H(Z)

BLAST

generator reaches zero. BLAST remains active as long as wait states are inserted

B(Z)

through the READY pin. BLAST becomes inactive after the final data transfer in a

R(1)

bus cycle.

is

DATA TRANSMIT/RECEIVE indicates direction for data transceivers. DT/R

O

used with DEN to provide control for data transceivers connected to the data bus.

DT/R is driven low to indicate the processor expects data (a read cycle). DT/R is

H(Z)

DT/R

driven high when the processor is “transmitting” data (a store cycle). DT/R only

B(Z)

changes state when DEN is high.

R(0)

0 = Data Receive

1 = Data Transmit

DATA ENABLE indicates data transfer cycles during a bus access.

is

DEN

asserted at the start of the first data cycle in a bus access and de-asserted at the

O

end of the last data cycle. DEN remains asserted for an entire bus request, even

when that request spans several bus accesses. For example, a ldq instruction

H(Z)

DEN

starting at an unaligned quad word boundary is one bus request spanning at least

B(Z)

two bus accesses. DEN remains asserted throughout all the accesses (including

R(1)

ADS states) and de-asserts when the Iqd instruction request is satisfied. DEN is

used with DT/R to provide control for data transceivers connected to the data bus.

DEN remains asserted for sequential reads from pipelined memory regions.

O

BUS LOCK indicates that an atomic read-modify-write operation is in progress.

LOCK may be used by the memory subsystem to prevent external agents from

H(Z)

LOCK

accessing memory that is currently involved in an atomic operation (e.g., a

B(Z)

semaphore). LOCK is asserted in the first clock of an atomic operation and de-

R(1)

asserted when BLAST is deasserted in the last bus cycle.

Datasheet 17