5 Language Reference

STATus:QUEStionable:ENABle <value>

STATus:QUEStionable:ENABle?

This command and its query set and read the value of the Questionable Enable register. This register is a mask for enabling specific bits from the Questionable Event register to set the questionable summary bit (QUES) of the Status Byte register. This bit (bit 3) is the logical OR of all the Questionable Event register bits that are enabled by the Questionable Status Enable register. The Preset value = 0.

STATus:QUEStionable:NTR <value>

STATus:QUEStionable:PTR <value>

STATus:QUEStionable:NTR?

STATus:QUEStionable:PTR?

These commands set or read the value of the Questionable NTR (Negative-Transition) and PTR (Positive-Transition) registers. These registers serve as polarity filters between the Questionable Condition and Questionable Event registers to cause the following actions:

When a bit of the Questionable NTR register is set to 1, then a 1- to-0 transition of the corresponding bit of the Questionable Condition register causes that bit in the Questionable Event register to be set.

When a bit of the Questionable PTR register is set to 1, then a 0- to-1 transition of the corresponding bit in the Questionable Condition register causes that bit in the Questionable Event register to be set.

If the same bits in both NTR and PTR registers are set to 1, then any transition of that bit at the Questionable Condition register sets the corresponding bit in the Questionable Event register.

If the same bits in both NTR and PTR registers are set to 0, then no transition of that bit at the Questionable Condition register can set the corresponding bit in the Questionable Event register.

The Preset values are: NTR = 0; PTR = 32767

*CLS

This command causes the following actions on the status system:

Clears the Standard Event Status, Operation Status Event, and

Questionable Status Event registers

Clears the Status Byte and the Error Queue

If *CLS immediately follows a program message terminator (<NL>), then the output queue and the MAV bit are also cleared.

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Series N5700 User’s Guide

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