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Agilent Technologies FS2331 user manual Read Burst Data Valid Position

Models: FS2331

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After these adjustments you should see an Eye Finder display like the above:

At this point you should make a note of the sampling position for the data lines. In the diagram above it is indicated as -2.45ns average for all data lines. This number will be used later when choosing the proper adjustment for the read burst delay line.

Step 3 – Read Burst Data Valid Position

For this step DDR bus activity must include a high frequency of read bursts. Memory tests or video clips are usually a good source of such activity. The read burst data valid position (not duration) is set by the delay line on the probe marked as “U18”. It is a 3 pin SIP. The factory setting for this is 1200ps +- 50ps. This setting should work well for 333Mhz DDR busses. If you are running your bus at 200Mhz you may find that a 1700ps value is more optimal. (Each delay line provided is marked with two digits

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Agilent Technologies FS2331 user manual Read Burst Data Valid Position

Contents

Revision DDR Sdram Analysis Probe FS2331How to reach us Product Warranty Signal Connections For Sales and Marketing Support For Technical SupportExclusive Remedies Product WarrantyLimitation of warranty Introduction Probe Cable, Connector NumberingDefinitions Logic Analyzer ModulesFS2331 100 pin Connector to Pod Diagram Probe Components Probe Feature SummaryFS2331 Probe Description Probe Design DDR CommandsState Clock Generation DDR DataPage Pod Clock Domain Clock Rate Probe Pod AssignmentOn closed Switch # Default factory Function PositionProbe Switch Settings Connecting Power to the FS2331 Probe Logic Analyzer Signal Threshold Voltage SettingsConnecting the Probe to the Logic Analyzer Card Requirements for PC2700 Systems Recommended Logic Analyzer Card Requirements16753/4/5/6 Setting up the 169xx Analyzer Setting up the 167xx AnalyzerSoftware Requirements System Software 169xx LicensingTiming Analysis All DDR speeds and supported analyzer cards Card Configurations for State Analysis Probing multiple DDR busses Interleaved memory If User is dedicating a Connecting to your Target System Chip Select§ Isolate the Dedicated DIMM’s pin Chip Select Jumper locations§ Sleeve the Pin Unused Pods § Wire from the adjacent Dimm slot to the isolated pinOffline Analysis Filtering Timing Analysis Operation Loading the Inverse Assembler and Decoding DDR CommandsState Analysis Operation Taking a Trace, Triggering, and Seeing Measurement ResultsInverse Assembler and Decoding DDR Commands Tracing the Serial Presence Detect Signals Using Eye Finder with the FS2331 DDR Probe Using EyeScan with the FS2331 Probe Dimm Signal Loading Option Using the FS2331 DDR Probe with an Interposer FS1024/25FS2331 Calibration Page Set Command sample position Page Page Write Burst Data Valid Position Page Page Page Read Burst Data Valid Position Page Page Page Set the final analyzer sample position Adjust the delay line value to maximize R/W overlapPage Standards supported General InformationSamtec Signal Connections J1 DataSA0 CB4 J2 Data and CommandSpare J3 Command and Data Buffcmdclk DM5DQS14 J4 DataDQS7