FS2331 Calibration | Agilent Technologies specification

FS2331 Calibration

The FS2331 is calibrated for operation at DDR333 rates, this should be sufficient for it’s operation. In the event that Data eye closure is seen during Eyefinder or Eyescan of simultaneous Writes and Reads, then the FS2331 calibration may need adjustment. The procedure below outlines this process.

If capture of both read and write bursts is required in a single measurement then special circuitry on the probe that deals with the different timing of read and write bursts must be checked. Depending on the results, the FS2331 must be calibrated along with setting the analyzer sample position. This specialized circuitry compensates for the differences in read and write timing by delaying the DQS0 strobe for reads. This ensures the data is stable (relative to the analyzer clock) at the same time for reads and writes. Use the following steps to determine if calibration steps are necessary for your application (probe, system board, and DIMM module).

To perform this check you should set the probe configuration switch (SW-6, On) to clock both read and write bursts to the analyzer, start your stimulus (that contains frequent read and write bursts) , and run Eye Finder. Below is a typical display

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Agilent Technologies user manual FS2331 Calibration

Contents

DDR Sdram Analysis Probe FS2331 Revision How to reach us Product Warranty Signal Connections For Technical Support For Sales and Marketing Support Exclusive Remedies Product WarrantyLimitation of warranty Probe Cable, Connector Numbering IntroductionDefinitions Logic Analyzer Modules FS2331 100 pin Connector to Pod Diagram Probe Components Probe Feature SummaryFS2331 Probe Description DDR Commands Probe DesignState Clock Generation DDR DataPage Probe Pod Assignment Pod Clock Domain Clock Rate On closed Switch # Default factory Function PositionProbe Switch Settings Connecting Power to the FS2331 Probe Logic Analyzer Signal Threshold Voltage SettingsConnecting the Probe to the Logic Analyzer Card Requirements for PC2700 Systems Recommended Logic Analyzer Card Requirements16753/4/5/6 Setting up the 167xx Analyzer Setting up the 169xx AnalyzerSoftware Requirements System Software 169xx Licensing Timing Analysis All DDR speeds and supported analyzer cards Card Configurations for State Analysis Probing multiple DDR busses Interleaved memory Connecting to your Target System Chip Select If User is dedicating a Chip Select Jumper locations § Isolate the Dedicated DIMM’s pin § Sleeve the Pin § Wire from the adjacent Dimm slot to the isolated pin Unused Pods Offline Analysis Filtering Loading the Inverse Assembler and Decoding DDR Commands Timing Analysis OperationState Analysis Operation Taking a Trace, Triggering, and Seeing Measurement Results Inverse Assembler and Decoding DDR Commands Tracing the Serial Presence Detect Signals Using Eye Finder with the FS2331 DDR Probe Using EyeScan with the FS2331 Probe Using the FS2331 DDR Probe with an Interposer FS1024/25 Dimm Signal Loading Option FS2331 Calibration Page Set Command sample position Page Page Write Burst Data Valid Position Page Page Page Read Burst Data Valid Position Page Page Page Adjust the delay line value to maximize R/W overlap Set the final analyzer sample positionPage General Information Standards supported Signal Connections J1 Data Samtec SA0 J2 Data and Command CB4 Spare J3 Command and Data Buffcmdclk J4 Data DM5DQS14 DQS7