Agilent Technologies FS2331 specification

Note: In the above picture under Logic analyzer pods, the first pod goes to the Odd pod and the second goes to the Even pod of the termination adapter (e.g. Pod B1 goes to odd termination adapter pod and B2 goes to the even termination adapter pod).

Configuration Files

167xx Analyzer

169xx Analyzer

State/Timing

Comment

	16717/8/9, 1675x	1675x, 1695x, 1691x	DR231_1	2 card timing

	16717/8/9, 1675x	1675x, 1695x, 1691x	DR231_2	3 card state analysis

	16717/8/9, 1675x	1675x, 1695x, 1691x	DR231_3	Two Interleaved DDR Banks, 5 cards
	16717/8/9, 1675x		DR231_3	required
				required

Timing Analysis (All DDR speeds and supported analyzer cards)

For timing analysis operation you need only two cards (except for the 16760, which requires four) regardless of supported card type or bus speed. These must be configured via the cables supplied with the cards as a single logic analyzer module. Refer to the appropriate Agilent Technologies manual for information on how to connect

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Agilent Technologies FS2331 user manual Timing Analysis All DDR speeds and supported analyzer cards

Contents

Revision DDR Sdram Analysis Probe FS2331 How to reach us Product Warranty Signal Connections For Sales and Marketing Support For Technical Support Exclusive Remedies Product WarrantyLimitation of warranty Introduction Probe Cable, Connector NumberingDefinitions Logic Analyzer Modules FS2331 100 pin Connector to Pod Diagram Probe Components Probe Feature SummaryFS2331 Probe Description Probe Design DDR CommandsState Clock Generation DDR DataPage Pod Clock Domain Clock Rate Probe Pod Assignment On closed Switch # Default factory Function PositionProbe Switch Settings Connecting Power to the FS2331 Probe Logic Analyzer Signal Threshold Voltage SettingsConnecting the Probe to the Logic Analyzer Card Requirements for PC2700 Systems Recommended Logic Analyzer Card Requirements16753/4/5/6 Setting up the 169xx Analyzer Setting up the 167xx AnalyzerSoftware Requirements System Software 169xx Licensing Timing Analysis All DDR speeds and supported analyzer cards Card Configurations for State Analysis Probing multiple DDR busses Interleaved memory If User is dedicating a Connecting to your Target System Chip Select § Isolate the Dedicated DIMM’s pin Chip Select Jumper locations § Sleeve the Pin Unused Pods § Wire from the adjacent Dimm slot to the isolated pin Offline Analysis Filtering Timing Analysis Operation Loading the Inverse Assembler and Decoding DDR CommandsState Analysis Operation Taking a Trace, Triggering, and Seeing Measurement Results Inverse Assembler and Decoding DDR Commands Tracing the Serial Presence Detect Signals Using Eye Finder with the FS2331 DDR Probe Using EyeScan with the FS2331 Probe Dimm Signal Loading Option Using the FS2331 DDR Probe with an Interposer FS1024/25 FS2331 Calibration Page Set Command sample position Page Page Write Burst Data Valid Position Page Page Page Read Burst Data Valid Position Page Page Page Set the final analyzer sample position Adjust the delay line value to maximize R/W overlapPage Standards supported General Information Samtec Signal Connections J1 Data SA0 CB4 J2 Data and Command Spare J3 Command and Data Buffcmdclk DM5DQS14 J4 Data DQS7