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Agilent Technologies
FS2331
user manual
Models:
FS2331
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Signal Connections
Warranty
Setting up the 167xx Analyzer
DDR Commands
Probe Switch Settings
Probe Feature Summary
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Contents
Revision
DDR Sdram Analysis Probe FS2331
How to reach us Product Warranty
Signal Connections
For Sales and Marketing Support
For Technical Support
Product Warranty
Limitation of warranty
Exclusive Remedies
Introduction
Probe Cable, Connector Numbering
Definitions
Logic Analyzer Modules
FS2331 100 pin Connector to Pod Diagram
Probe Feature Summary
FS2331 Probe Description
Probe Components
Probe Design
DDR Commands
State Clock Generation
DDR Data
Page
Pod Clock Domain Clock Rate
Probe Pod Assignment
Switch # Default factory Function Position
Probe Switch Settings
On closed
Logic Analyzer Signal Threshold Voltage Settings
Connecting the Probe to the Logic Analyzer
Connecting Power to the FS2331 Probe
Card Requirements for PC2700 Systems
Logic Analyzer Card Requirements
16753/4/5/6
Recommended
Setting up the 169xx Analyzer
Setting up the 167xx Analyzer
Software Requirements System Software
169xx Licensing
Timing Analysis All DDR speeds and supported analyzer cards
Card Configurations for State Analysis
Probing multiple DDR busses Interleaved memory
If User is dedicating a
Connecting to your Target System Chip Select
§ Isolate the Dedicated DIMM’s pin
Chip Select Jumper locations
§ Sleeve the Pin
Unused Pods
§ Wire from the adjacent Dimm slot to the isolated pin
Offline Analysis
Filtering
Timing Analysis Operation
Loading the Inverse Assembler and Decoding DDR Commands
State Analysis Operation
Taking a Trace, Triggering, and Seeing Measurement Results
Inverse Assembler and Decoding DDR Commands
Tracing the Serial Presence Detect Signals
Using Eye Finder with the FS2331 DDR Probe
Using EyeScan with the FS2331 Probe
Dimm Signal Loading Option
Using the FS2331 DDR Probe with an Interposer FS1024/25
FS2331 Calibration
Page
Set Command sample position
Page
Page
Write Burst Data Valid Position
Page
Page
Page
Read Burst Data Valid Position
Page
Page
Page
Set the final analyzer sample position
Adjust the delay line value to maximize R/W overlap
Page
Standards supported
General Information
Samtec
Signal Connections J1 Data
SA0
CB4
J2 Data and Command
Spare
J3 Command and Data
Buffcmdclk
DM5DQS14
J4 Data
DQS7
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