Albatron Technology ARM11/Cortex-A8 user manual CPxx Registers, CP15 Cache Type CRn = 0, opcode2 =

bdiGDB for GNU Debugger, BDI2000 (ARM11/Cortex-A8) User Manual 46

3.4.2 CPxx Registers

Via Telnet it is possible to access the Coprocessor 15,14,13 registers. Following the Telnet com- mands that are used to access CP registers:

"RDCP	<number>		display control processor 15		register",
"RDCP 15 <number>			display control processor 15		register",
"RDCP 14 <number>			display control processor 14		register",
"RDCP 13 <number>			display control processor 13		register",
	....
"RMCP	<number>	<value>	modify control processor 15	register",
"RMCP 15 <number>		<value>	modify control processor 15	register",
"RMCP 14 <number>		<value>	modify control processor 14	register",
"RMCP 13 <number>		<value>	modify control processor 13	register",
	....

The parameter number selects the CPxx register. This parameter is used to build the appropriate MCR or MRC instruction.

+-----	+-+-------	+-----	+-+-------	+
opc_20		CRm opc_10		nbr
+-----	+-+-------	+-----	+-+-------	+

Some examples:

CP15 : ID register (CRn = 0, opcode_2 = 0)

BDI> rdcp 15 0x0000

CP15 : Cache Type (CRn = 0, opcode_2 = 1)

BDI> rdcp 15 0x2000

CP15 : Invalidate I cache line (CRn = 7, opcode_2 = 1, CRm = 5)

BDI> rmcp 15 0x2507 0xA0000000

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