PRELIMINARYCY14B101P

Hardware STORE Cycle

Parameter

 

 

Description

 

 

 

 

tDHSB

 

 

To Output Active Time when write latch not set

HSB

tPHSB

 

Hardware STORE Pulse Width

 

 

 

Figure 30. Hardware STORE Cycle[9]

 

CY14B101P

Unit

Min

 

Max

 

 

 

 

25

ns

15

 

 

ns

 

 

 

 

Write Latch set

tPHSB

HSB (IN)

tDELAY

HSB (OUT)

SO

RWI

~~ tSTORE

~~

~

 

~

tHHHD

tLZHSB

Write Latch not set

tPHSB

HSB (IN)

HSB

(OUT)

tDELAY

 

 

RWI

 

~ ~

tDHSB

HSB pin is driven high to VCC only by Internal 100K: resistor, HSB driver is disabled

SRAM is disabled as long as HSB (IN) is driven LOW.

tDHSB

~ ~

Document #: 001-44109 Rev. *B

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Cypress CY14B101P manual Hardware Store Cycle, Parameter Description, To Output Active Time when write latch not set