PRELIMINARY CY14B101P
Document #: 001-44109 Rev. *B Page 3 of 32
Device Operation
CY14B101P is a 1-Mbit nvSRAM memory with integrated RTC
and SPI interface. All the reads and writes to nvSRAM happen
to the SRAM which gives nvSRAM the unique capability to
handle infinite writes to the memory. The data in SRAM is
secured by a STORE sequence that transfers the data in parallel
to the nonvolatile Quantum Trap cells. A small capacitor (V
CAP
)
is used to AutoStore the SRAM data in nonvolatile cells when
power goes down providing power down data security. The
Quantum Trap nonvolatile elements built in the reliable SONOS
technology make nvSRAM the ideal choice for secure data
storage.
In CY14B101P, the 1-Mbit memory array is organized as
128K words x 8 bits. The memory is accessed through a
standard SPI interface that enables very high clock speeds upto
40 MHz with zero delay read and write cycles. CY14B101P
supports SPI modes 0 and 3 (CPOL, CPHA = 0, 0 & 1, 1) and
operates as SPI slave. The device is enabled using the Chip
Select pin (CS) and accessed through Serial Input (SI), Serial
Output (SO), and Serial Clock (SCK) pins.
CY14B101P provides the feature for hardware and software
write protection through WP pin and WRDI instruction.
CY14B101P also provides mechanisms for block write
protection (1/4, 1/2, or full array) using BP0 and BP1 pins in the
status register. Further, the HOLD pin is used to suspend any
serial communication without resetting the serial sequence.
CY14B101P uses the standard SPI opcodes for memory access.
In addition to the general SPI instructions for read and write,
CY14B101P provides four special instructions that allow access
to four nvSRAM specific functions: STORE, RECALL, AutoStore
Disable (ASDISB), and AutoStore Enable (ASENB).
The major benefit of nvSRAM SPI over serial EEPROMs is that
all reads and writes to nvSRAM are performed at the speed of
SPI bus with zero cycle delay. Therefore, no wait time is required
after any of the memory accesses. The STORE and RECALL
operations need finite time to complete and all memory accesses
are inhibited during this time. While a STORE or RECALL
operation is in progress, the busy status of the device is indicated
by the Hardware Store Busy (HSB) pin and also reflected on the
RDY bit of the Status Register.

SRAM Write

All writes to nvSRAM are carried out on the SRAM and do not
use up any endurance cycles of the nonvolatile memory. This
enables user to perform infinite write operations. A write cycle is
performed through the SPI WRITE instruction. The WRITE
instruction is issued through the SI pin of the nvSRAM and
consists of the WRITE opcode, 3 bytes of address and 1 byte of
data. Writes to nvSRAM is done at SPI bus speed with zero cycle
delay.
CY14B101P allows burst mode writes to be performed through
SPI. This enables write operations on consecutive addresses
without issuing a new WRITE instruction. When the last address
in memory is reached in burst mode, the address rolls over to
0x0000 and the device continues to write.
The SPI write cycle sequence is defined in the Memory Access
section of SPI Protocol Description.

SRAM Read

A read cycle in CY14B101P is performed at the SPI bus speed
and the data is read out with zero cycle delay after the READ
instruction is performed. The READ instruction is issued through
the SI pin of the nvSRAM and consists of the READ opcode and
3 bytes of address. The data is read out on the SO pin.
CY14B101P allows burst mode reads to be performed through
SPI. This enables reads on consecutive addresses without
issuing a new READ instruction. When the last address in
memory is reached in burst mode read, the address rolls over to
0x0000 and the device continues to read.
The SPI read cycle sequence is defined in the Memory Access
section of SPI Protocol Description

STORE Operation

STORE operation transfers the data from the SRAM to the
nonvolatile Quantum Trap cells. The CY14B101P STOREs data
to the nonvolatile cells using one of the three STORE operations:
AutoStore, activated on device power down; Software Store,
activated by a STORE instruction in the SPI; and Hardware
Store, activated by the HSB. During the STORE cycle, an erase
of the previous nonvolatile data is first performed, followed by a
program of the nonvolatile elements. After a STORE cycle is
initiated, further input and output are disabled until the cycle is
completed.
The HSB signal or the RDY bit in the Status register can be
monitored by the system to detect if a STORE cycle is in
progress. The busy status of nvSRAM is indicated by HSB being
pulled LOW or RDY bit being set to ‘1’. To avoid unnecessary
nonvolatile STOREs, AutoStore and Hardware Store operations
are ignored unless at least one write operation has taken place
since the most recent STORE or RECALL cycle. However,
software initiated STORE cycles are performed regardless of
whether a write operation has taken place.

AutoStore Operation

The AutoStore operation is a unique feature of nvSRAM which
automatically stores the SRAM data to QuantumTrap during
power down. This STORE mechanism is implemented using a
capacitor (V
CAP
) and enables the device to safely STORE the
data in the nonvolatile memory when power goes down.
During normal operation, the device draws current from V
CC
to
charge the capacitor connected to the V
CAP
pin. When the
voltage on the V
CC
pin drops below V
SWITCH
during power down,
the device inhibits all memory accesses to nvSRAM and
automatically performs a conditional STORE operation using the
charge from the V
CAP
capacitor. The AutoStore operation is not
initiated if no write cycle has been performed since last RECALL.
During power down, the memory accesses are inhibited after the
voltage on V
CC
pin drops below V
SWITCH
. To avoid inadvertent
writes, ensure that CS is not left floating prior to this event.
Therefore, during power down the device must be deselected
and CS must be allowed to follow V
CC
.
Figure 2 shows the proper connection of the storage capacitor
(V
CAP
) for AutoStore operation. Refer to DC Electrical Charac-
teristics on page 22 for the size of the V
CAP
.
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