Cypress CY14B101P PRELIMINARY CY14B101P

PRELIMINARY CY14B101P

Document #: 001-44109 Rev. *B Page 14 of 32

Real Time Clock Operation

nvTIME Operation

The CY14B101P offers internal registers that contain clock,

alarm, watchdog, interrupt, and control functions. The RTC

registers occupy a separate address space from nvSRAM and

are accessible through Read RTC (RDRTC) and Write RTC

(WRTC) instructions on register addresses 0x00 to 0x0F. Internal

double buffering of the clock and the timer information registers

prevents accessing transitional internal clock data during a read

or write operation. Double buffering also circumvents disrupting

normal timing counts or the clock accuracy of the internal clock

when accessing clock data. Clock and alarm registers store data

in BCD format.

Clock Operations

The clock registers maintain time up to 9,999 years in

one-second increments. The time can be set to any calendar

time and the clock automatically keeps track of days of the week

and month, leap years, and century transitions. There are eight

registers dedicated to the clock functions, which are used to set

time with a write cycle and to read time during a read cycle.

These registers contain the time of day in BCD format. Bits

defined as ‘0’ are currently not used and are reserved for future

use by Cypress.

Reading the Clock

The double buffered RTC register structure reduces the chance

of reading incorrect data from the clock. The user must stop

internal updates to the CY14B101P time keeping registers

before reading clock data, to prevent reading of data in transition.

Stopping the register updates does not affect clock accuracy.

The updating process is stopped by writing a ‘1’ to the read bit

‘R’ (in the flags register at 0x00), and does not restart until a ‘0’

is written to the read bit. The RTC registers are read while the

internal clock continues to run. After a ‘0’ is written to the read bit

(‘R’), all RTC registers are simultaneously updated within 20 ms.

Setting the Clock

Setting the write bit ‘W’ (in the flags register at 0x00) to a ‘1’ stops

updates to the time keeping registers and enables the time to be

set. The correct day, date, and time is then written into the

registers and must be in 24-hour BCD format. The time written

is referred to as the “Base Time”. This value is stored in nonvol-

atile registers and used in the calculation of the current time.

Resetting the write bit to ‘0’ transfers the values of timekeeping

registers to the actual clock counters, after which the clock

resumes normal operation.

If the time written to the timekeeping registers is not in the correct

BCD format, each invalid nibble of the RTC registers continue

counting to 0xF before rolling over to 0x0 after which RTC

resumes normal operation.

Note The values entered in the timekeeping, alarm, calibration,

and interrupt registers must be saved to nonvolatile memory by

a STORE operation. Therefore, while working in AutoStore

disabled mode, perform a STORE operation after writing into the

RTC registers for the modifications to be correctly recorded.

Backup Power

The RTC in the CY14B101P is intended for permanently

powered operation. The V

RTCcap

or V

RTCbat

pin is connected

depending on whether a capacitor or battery is chosen for the

application. When the primary power, V

, fails and drops below

SWITCH

the device switches to the backup power supply.

The clock oscillator uses very little current, which maximizes the

backup time available from the backup source. Regardless of the

clock operation with the primary source removed, the data stored

in the nvSRAM is secure, having been stored in the nonvolatile

elements when power was lost.

During backup operation, the CY14B101P consumes a

maximum of 300 nanoamps at room temperature. The user must

choose capacitor or battery values according to the application.

Backup time values based on maximum current specifications

are shown in the following table. Nominal backup times are

approximately two times longer.

Using a capacitor has the obvious advantage of recharging the

backup source each time the system is powered up. If a battery

is used, a 3V lithium is recommended and the CY14B101P

sources current only from the battery when the primary power is

removed. However, the battery is not recharged at any time by

the CY14B101P. The battery capacity must be chosen for total

anticipated cumulative down time required over the life of the

system.

Stopping and Starting the Oscillator

The OSCEN bit in the calibration register at 0x08 controls the

enable and disable of the oscillator. This bit is nonvolatile and is

shipped to customers in the “enabled” (set to 0) state. To

preserve the battery life when the system is in storage, OSCEN

must be set to ‘1’. This turns off the oscillator circuit, extending

the battery life. If the OSCEN bit goes from disabled to enabled,

it takes approximately one second (two seconds maximum) for

the oscillator to start.

While system power is off, If the voltage on the backup supply

RTCcap

or V

RTCbat

) falls below their respective minimum level,

the oscillator may fail.The CY14B101P has the ability to detect

oscillator failure when system power is restored. This is recorded

in the OSCF (Oscillator Failed bit) of the flags register at the

address 0x00. When the device is powered on (V

goes above

SWITCH

) the OSCEN bit is checked for “enabled” status. If the

OSCEN bit is enabled and the oscillator is not active within the

first 5 ms, the OSCF bit is set to “1”. The system must check for

this condition and then write ‘0’ to clear the flag. Note that in

addition to setting the OSCF flag bit, the time registers are reset

to the “Base Time” (see Setting the Clock on page 14), which is

the value last written to the timekeeping registers. The control or

calibration registers and the OSCEN bit are not affected by the

‘oscillator failed’ condition.

Table 8. RTC Backup Time

Capacitor Value Backup Time

0.1F 72 hours

0.47F 14 days

1.0F 30 days

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