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CY14B101P
- page 30
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32 pages, 995.69 Kb
PRELIMINARY
CY14B101P
Document #: 001-44109 Rev. *B
Page 30 of 32
Package Diagrams
Figure 31. 16-Pin (300 mil) SOIC Package (51-85022)
51-85022 *B
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Contents
Main
PRELIMINARY CY14B101P
1 Mbit (128K x 8) Serial SPI nvSRAM with Real Time Clock
,
Features
Overview
Logic Block Diagram
Pinouts
Device Operation
SRAM Write
SRAM Read
STORE Operation
AutoStore Operation
PRELIMINARY CY14B101P
Software Store Operation
Hardware Store and HSB pin Operation
RECALL Operation
Hardware Recall (Power Up)
Page
SPI Modes
SPI Operating Features
Power Up
Power On Reset
Power Down
Active Power and Standby Power Modes
Status Register
Read Status Register (RDSR) Instruction
Write Status Register (WRSR) Instruction
Write Protection and Block Protection
Write Enable (WREN) Instruction
Write Disable (WRDI) Instruction
Block Protection
Hardware Write Protection (WP Pin)
PRELIMINARY CY14B101P
Memory Access
Read Sequence (READ)
Write Sequence (WRITE)
READ RTC (RDRTC) Instruction
WRITE RTC (WRTC) Instruction
nvSRAM Special Instructions
Software Store (STORE)
Software Recall (RECALL)
AutoStore Disable (ASDISB)
AutoStore Enable (ASENB)
HOLD Pin Operation
PRELIMINARY CY14B101P
Real Time Clock Operation
nvTIME Operation
Clock Operations
Reading the Clock
Calibrating the Clock
Alarm
Watchdog Timer
Power Monitor
Interrupts
Interrupt Register
Flags Register
Accessing the Real Time Clock through SPI
Page
Page
Page
Page
Maximum Ratings
DC Electrical Characteristics
AC Test Conditions
Data Retention and Endurance
Capacitance
Thermal Resistance
AC Switching Characteristics
Document #: 001-44109 Rev. *B Page 25 of 32
Figure 25. Synchronous Data Timing (Mode 0)
Figure 26. HOLD Timing
~
AutoStore or Power Up RECALL
Switching Waveforms
Software Controlled STORE/RECALL Cycles
Page
Ordering Information
Part Numbering Nomenclature
Page
Document History Page
Sales, Solutions, and Legal Information
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PSoC Solutions