Cypress CY14B101P manual SPI Modes, System Configuration Using SPI nvSRAM

PRELIMINARYCY14B101P

Figure 3. System Configuration Using SPI nvSRAM

S C K
M O S I
M IS O
S C K	S I	S O	S C K	S I	S O
u C o n tro lle r
C Y 1 4B 10 1 P			C Y 1 4 B 1 0 1P
C S		H O L D	C S		H O L D
C S 1
H O L D 1
C S 2
H O L D 2

SPI Modes

CY14B101P device may be driven by a microcontroller with its SPI peripheral running in either of the following two modes:

■SPI Mode 0 (CPOL=0, CPHA=0)

■SPI Mode 3 (CPOL=1, CPHA=1)

For both these modes, input data is latched in on the rising edge of Serial Clock (SCK) starting from the first rising edge after CS goes active. If the clock starts from a HIGH state (in mode 3), the first rising edge after the clock toggles are considered. The output data is available on the falling edge of Serial Clock (SCK).

Figure 4. SPI Mode 0

CS
	0	1	2	3	4	5		6	7
SCK
SI	7	6	5	4	3	2	1		0

MSBLSB

The two SPI modes are shown in Figure 4 and Figure 5. The status of clock when the bus master is in Standby mode and not transferring data is:

■SCK remains at 0 for Mode 0

■SCK remains at 1 for Mode 3

CPOL and CPHA bits must be set in the SPI controller for the either Mode 0 or Mode 3. CY14B101P detects the SPI mode from the status of SCK pin when device is selected by bringing the CS pin LOW. If SCK pin is LOW when device is selected, SPI Mode 0 is assumed and if SCK pin is HIGH, CY14B101P works in SPI Mode 3.

Figure 5. SPI Mode 3

CS

0 1 2 3 4 5 6 7

SCK

SI 7 6 5 4 3 2 1 0

MSBLSB

Document #: 001-44109 Rev. *B Page 6 of 32

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