
CY7C1440AV33
CY7C1442AV33
CY7C1446AV33
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM
Features
•Supports bus operation up to 250 MHz
•Available speed grades are 250, 200 and 167 MHz
•Registered inputs and outputs for pipelined operation
•3.3V core power supply
•2.5V/3.3V I/O power supply
•Fast
— 2.6 ns (for
•Provide
•
•Separate processor and controller address strobes
•Synchronous
•Asynchronous output enable
•Single Cycle Chip Deselect
•CY7C1440AV33, CY7C1442AV33 available in
•Also available in
•IEEE 1149.1
•“ZZ” Sleep Mode Option
Functional Description[1]
The CY7C1440AV33/CY7C1442AV33/CY7C1446AV33 SRAM integrates 1M x 36/2M x 18 and 512K x 72 SRAM cells with advanced synchronous peripheral circuitry and a
Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor (ADSP) or Address Strobe Controller (ADSC) are active. Subsequent burst addresses can be internally generated as controlled by the Advance pin (ADV).
Address, data inputs, and write controls are registered
The CY7C1440AV33/CY7C1442AV33/CY7C1446AV33 operates from a +3.3V core power supply while all outputs may operate with either a +2.5 or +3.3V supply. All inputs and outputs are
Selection Guide
| 250 MHz | 200 MHz | 167 MHz | Unit |
Maximum Access Time | 2.6 | 3.2 | 3.4 | ns |
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Maximum Operating Current | 475 | 425 | 375 | mA |
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Maximum CMOS Standby Current | 120 | 120 | 120 | mA |
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Note:
1. For
Cypress Semiconductor Corporation | • | 198 Champion Court • San Jose, CA | • | |
Document #: |
| Revised June 23, 2006 |
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