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Cypress CY7C1446AV33, CY7C1440AV33, CY7C1442AV33 manual Pin Definitions, Name Description

Models: CY7C1440AV33 CY7C1446AV33 CY7C1442AV33

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CY7C1440AV33

CY7C1442AV33

CY7C1446AV33

Pin Configurations (continued)

209-ball FBGA (14 x 22 x 1.76 mm) Pinout CY7C1446AV33 (512K × 72)

1

2

3

4

5

6

7

8

9

10

11

A

DQG

DQG

A

CE2

A

DQB

ADSP

ADSC

ADV

CE

3

DQB

B

DQG

DQG

A

DQ

DQ

NC/288M

BWS

BWS

C

BWS

G

BW

B

BWS

F

B

B

C

DQG

DQG

NC/144M

NC/576M

DQ

BWS

H

BWS

D

CE

1

BWS

E

BWS

A

B

DQB

D

DQG

DQG

VSS

NC/1G

NC

NC

OE

GW

VSS

DQ

DQ

B

B

E

DQPG

DQPC

VDDQ

VDDQ

VDD

VDD

VDD

VDDQ

VDDQ

DQP

DQP

F

B

F

DQC

DQC

VSS

VSS

VSS

NC

VSS

VSS

VSS

DQF

DQF

G

DQC

DQC

VDDQ

VDDQ

VDD

NC

VDD

VDDQ

VDDQ

DQ

DQ

F

F

H

DQC

DQ

C

V

SS

VSS

VSS

NC

VSS

VSS

VSS

DQ

DQF

F

J

DQC

DQC

VDDQ

VDDQ

VDD

NC

VDD

VDDQ

VDDQ

DQF

DQF

K

NC

NC

CLK

NC

VSS

VSS

VSS

NC

NC

NC

NC

L

DQH

DQH

VDDQ

VDDQ

VDD

NC

VDD

VDDQ

VDDQ

DQ

A

DQ

A

M

DQH

DQH

VSS

VSS

VSS

NC

VSS

VSS

VSS

DQA

DQA

N

DQH

DQH

VDDQ

VDDQ

VDD

NC

VDD

VDDQ

VDDQ

DQA

DQA

P

DQH

DQH

VSS

VSS

VSS

ZZ

VSS

VSS

VSS

DQA

DQA

R

DQP

DQP

H

VDDQ

V

DDQ

V

DD

V

DD

V

DD

V

DDQ

V

DDQ

DQP

DQP

D

E

A

T

DQD

DQD

VSS

NC

NC

MODE

NC

NC

VSS

DQE

DQE

U

DQD

DQD

NC/72M

A

A

A

A

A

A

DQ

DQ

E

E

V

DQD

DQD

A

A

A

A1

A

A

A

DQE

DQE

W

DQD

DQD

TMS

TDI

A

A0

A

TDO

TCK

DQE

DQE

Pin Definitions

Name

I/O

Description

A0, A1, A

Input-

Address Inputs used to select one of the address locations. Sampled at the rising edge

Synchronous

of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3[2]are sampled active.

A1: A0 are fed to the two-bit counter.

A,

B,

Input-

BW

BW

Byte Write Select Inputs, active LOW. Qualified with

to conduct byte writes to the

BWE

BWC, BWD,

Synchronous

SRAM. Sampled on the rising edge of CLK.

BWE, BWF,

BWG, BWH

Input-

Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK,

GW

Synchronous

a global write is conducted (ALL bytes are written, regardless of the values on BWX and

BWE).

Input-

Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal

BWE

Synchronous

must be asserted LOW to conduct a byte write.

CLK

Input-

Clock Input. Used to capture all synchronous inputs to the device. Also used to increment

Clock

the burst counter when ADV is asserted LOW, during a burst operation.

1

Input-

Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction

CE

Synchronous

with CE2 and CE3 to select/deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is

sampled only when a new external address is loaded.

Document #: 38-05383 Rev. *E

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Cypress CY7C1446AV33, CY7C1440AV33 Pin Definitions, Name Description, Byte Write Select Inputs, active LOW. Qualified with

Contents

Selection Guide FeaturesFunctional Description1 250 MHz 200 MHz 167 MHz UnitLogic Block Diagram CY7C1440AV33 1M x Logic Block Diagram CY7C1442AV33 2M xCY7C1440AV33 Pin Configurations Pin Tqfp Pinout CY7C1442AV33 2M xCY7C1442AV33 2M x Pin Definitions Name DescriptionByte Write Select Inputs, active LOW. Qualified with Ground for the core of the device Power supply inputs to the core of the devicePower supply for the I/O circuitry Ground for the I/O circuitryFunctional Overview Interleaved Burst Address Table Mode = Floating or VDD Linear Burst Address Table Mode = GNDZZ Mode Electrical Characteristics Write Cycle, Suspend Burst Truth Table for Read/Write4,8,9Truth Table for Read/Write4, 8 Function CY7C1440AV33TAP Controller State Diagram TAP Controller Block DiagramIeee 1149.1 Serial Boundary Scan Jtag Performing a TAP Reset TAP RegistersTAP Instruction Set TAP Timing Bypass5V TAP AC Test Conditions TAP AC Switching Characteristics Over the operating Range103V TAP AC Test Conditions 5V TAP AC Output Load EquivalentScan Register Sizes TAP DC Electrical Characteristics And Operating ConditionsIdentification Register Definitions Identification CodesBypass Ball Fbga Boundary Scan Order 14,15SAMPLE/PRELOAD CY7C1440AV33 1M x 36, CY7C1442AV33 2M x Bit # Ball IDBall Fbga Boundary Scan Order 14 CY7C1446AV33 512K x Bit # Ball IDOperating Range Electrical Characteristics Over the Operating Range17Maximum Ratings Ambient RangeCapacitance19 Thermal ResistanceAC Test Loads and Waveforms Min Max Switching Characteristics Over the Operating Range 24250 200 167 Parameter Description Unit Min Set-up TimesSwitching Waveforms Read Cycle Timing26Write Cycle Timing26 Read/Write Cycle Timing26, 28 CLZZZ Mode Timing30 DON’T CareOrdering Information 250 Package Diagrams Pin Tqfp 14 x 20 x 1.4 mmBall Fbga 15 x 17 x 1.4 mm Ball Fbga 14 x 22 x 1.76 mm Issue Date Orig. Description of Change Document HistoryDocument Number 473650 AC Switching Characteristics tableUpdated the Ordering Information table VKN