CY7C1440AV33

CY7C1442AV33

CY7C1446AV33

Switching Waveforms

Read Cycle Timing[26]

tCYC

CLK

tCH

tADS tADH

ADSP

ADSC

tAS tAH

tCL

tADS tADH

ADDRESS

GW, BWE, BWx

A1

A2

A3

tWES tWEH

Burst continued with

new base address

tCES

tCEH

 

 

 

 

 

 

 

Deselect

 

 

 

 

 

 

 

cycle

 

 

 

 

 

 

 

 

 

CE

 

 

 

 

 

 

 

 

 

 

 

tADVS

tADVH

 

 

 

 

 

 

ADV

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ADV

 

 

 

 

 

 

 

 

 

suspends

 

 

 

 

 

 

 

 

 

burst.

 

 

 

 

OE

 

 

 

 

 

 

 

 

 

 

 

 

tOEV

tCO

 

 

 

 

 

 

 

tOEHZ

tOELZ

tDOH

 

 

 

 

tCHZ

 

 

tCLZ

 

 

 

 

 

 

 

Data Out (Q)

High-Z

Q(A1)

 

Q(A2)

Q(A2 + 1)

Q(A2 + 2)

Q(A2 + 3)

Q(A2)

Q(A2 + 1)

 

 

tCO

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Burst wraps around

 

 

 

 

 

 

 

 

to its initial state

 

 

Single READ

 

 

 

BURST READ

 

 

 

 

 

 

 

DON’T CARE

UNDEFINED

 

 

 

 

Note:

26. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.

Document #: 38-05383 Rev. *E

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Cypress CY7C1446AV33, CY7C1440AV33, CY7C1442AV33 manual Switching Waveforms, Read Cycle Timing26