Cypress CY7C1440AV33, CY7C1442AV33, CY7C1446AV33 , CY7C1442AV33

CY7C1440AV33
CY7C1442AV33
CY7C1446AV33
Document #: 38-05383 Rev. *E Page 2 of 31
Logic Block Diagram – CY7C1440AV33 (1M x 36)
ADDRESS
REGISTER
ADV
CLK BURST
COUNTER
AND
LOGIC
CLR
Q1
Q0
ADSP
ADSC
MODE
BWE
GW
CE 1
CE 2
CE 3
OE
ENABLE
REGISTER
OUTPUT
REGISTERS
SENSE
AMPS
OUTPUT
BUFFERS
E
PIPELINED
ENABLE
INPUT
REGISTERS
A
0, A1, A
BW B
BW C
BW D
BW A
MEMORY
ARRAY
DQs
DQPA
DQPB
DQPC
DQPD
SLEEP
CONTROL
ZZ
A [1:0]
2
DQ A , DQP A
BYTE
WRITE REGISTER
DQ
B , DQP B
BYTE
WRITE REGISTER
DQ
C , DQP C
BYTE
WRITE REGISTER
DQ
D , DQP D
BYTE
WRITE REGISTER
DQ
A , DQP A
BYTE
WRITE DRIVER
DQ
B , DQP B
BYTE
WRITE DRIVER
DQ
C , DQP C
BYTE
WRITE DRIVER
DQ
D ,DQP D
BYTE
WRITE DRIVER
A
0, A1, A ADDRESS
REGISTER
ADV
CLK BURST
COUNTER AND
LOGIC
CLR
Q1
Q0
ADSC
BWB
BWA
CE1
DQB,DQPB
WRITE REGISTER
DQA,DQPA
WRITE REGISTER
ENABLE
REGISTER
OE
SENSE
AMPS
MEMORY
ARRAY
ADSP
2
MODE
CE2
CE3
GW
BWE
PIPELINED
ENABLE
DQs
DQP
A
DQP
B
OUTPUT
REGISTERS
INPUT
REGISTERS
E
DQA,DQPA
WRITE DRIVER
OUTPUT
BUFFERS
DQB,DQPB
WRITE DRIVER
A[1:0]
ZZ SLEEP
CONTROL
Logic Block Diagram – CY7C1442AV33 (2M x 18)
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