Cypress CY7C1440AV33, CY7C1442AV33, CY7C1446AV33

CY7C1440AV33

CY7C1442AV33

CY7C1446AV33

Document #: 38-05383 Rev. *E Page 31 of 31

*E 473650 See ECN VKN Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND.

Changed tTH, tTL from 25 ns to 20 ns and tTDOV from 5 ns to 10 ns in TAP

AC Switching Characteristics table.

Updated the Ordering Information table.

Document Title: CY7C1440AV33/CY7C1442AV33/CY7C1446AV3336-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync

SRAM

Document Number: 38-05383

REV. ECN NO. Issue Date Orig. of

Change Description of Change

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Contents

Main 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM CY7C1440AV33 CY7C1442AV33 CY7C1446AV33 Features Functional Description Selection Guide CY7C1442AV33 WRITE DRIVER WRITE DRIVER E CY7C1440AV33 CY7C1442AV33 CY7C1446AV33 BYTE ADSC Document #: 38-05383 Rev. *E Page 3 of 31 CY7C1440AV33 CY7C1442AV33 CY7C1446AV33 Pin Configurations CY7C1440AV33 (1M x 36) CY7C1442AV33 (2M x 18) Pin Configurations 165-ball FBGA (15 x 17 x 1.4 mm) Pinout CY7C1440AV33 (1M x 36) 2345671 A B C D E F G H J K L M N P R CY7C1442AV33 (2M x 18) 891011 2345671 A B C D E F G H J K L M N P R CY7C1446AV33 DQP 209-ball FBGA (14 x 22 x 1.76 mm) Pinout CY7C1446AV33 (512K 72) Pin Configurations CY7C1440AV33 CY7C1442AV33 CY7C1446AV33 Pin Definitions Functional Overview Interleaved Burst Address Table (MODE = Floating or VDD) Linear Burst Address Table (MODE = GND) ZZ Mode Electrical Characteristics Truth Table Truth Table for Read/Write IEEE 1149.1 Serial Boundary Scan (JTAG) TAP Controller State Diagram TAP Controller Block Diagram Truth Table for Read/Write Page TAP Timing CY7C1440AV33 CY7C1442AV33 CY7C1446AV33 F DO T TAP DC Electrical Characteristics And Operating Conditions Identification Register Definitions Scan Register Sizes Identification Codes 165-ball FBGA Boundary Scan Order 209-ball FBGA Boundary Scan Order Maximum Ratings Operating Range Electrical Characteristics Capacitance Thermal Resistance AC Test Loads and Waveforms Switching Characteristics Switching Waveforms Read Cycle Timing Write Cycle Timing Note: 27.Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BWX LOW. Read/Write Cycle Timing ZZ Mode Timing Page Ordering Information Package Diagrams A 100-pin TQFP (14 x 20 x 1.4 mm) (51-85050) Package Diagrams 165-ball FBGA (15 x 17 x 1.4 mm) (51-85165) 51-85165-*A Page Document History Page