Cypress CY7C1440AV33, CY7C1442AV33, CY7C1446AV33 , CY7C1440AV33 CY7C1442AV33 CY7C1446AV33

CY7C1440AV33
CY7C1442AV33
CY7C1446AV33
Document #: 38-05383 Rev. *E Page 3 of 31
BWD
BWC
BWB
BWA
BWE
GW
CE1
CE2
CE3
OE
ENABLE
REGISTER PIPELINED
ENABLE
ADDRESS
REGISTER
ADV
CLK BINARY
COUNTER
CLR
Q1
Q0
ADSP
ADSC
MODE
A
0, A1,A
A[1:0]
BWF
BWE
BWH
BWG
DQs
DQP
A
DQP
B
DQP
C
DQP
D
DQP
E
DQP
F
DQP
G
DQP
H
OUTPUT
REGISTERS
MEMORY
ARRAY
OUTPUT
BUFFERS
E
DQA, DQPA
WRITE DRIVER
DQB, DQPB
WRITE DRIVER
DQC, DQPC
WRITE DRIVER
DQD, DQPD
WRITE DRIVER
INPUT
REGISTERS
BYTE “a”
WRITE DRIVER
DQE, DQPE
WRITE DRIVER
DQF, DQPF
WRITE DRIVER
DQG, DQPG
WRITE DRIVER
DQH, DQPH
WRITE DRIVER
SENSE
AMPS
SLEEP
CONTROL
ZZ
DQA, DQPA
WRITE DRIVER
DQB, DQPB
WRITE DRIVER
DQC, DQPC
WRITE DRIVER
DQD, DQPD
WRITE DRIVER
DQE, DQPE
WRITE DRIVER
DQF, DQPF
WRITE DRIVER
DQF, DQPF
WRITE DRIVER
DQH, DQPH
WRITE DRIVER
Logic Block Diagram – CY7C1446AV33 (512K x 72)
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