CY7C1440AV33

CY7C1442AV33

CY7C1446AV33

Switching Waveforms (continued)

Read/Write Cycle Timing[26, 28, 29]

 

 

 

tCYC

CLK

 

 

 

 

 

tCH

tCL

 

tADS

tADH

 

ADSP

 

 

 

ADSC

 

 

 

 

tAS

tAH

 

ADDRESS

A1

A2

 

BWE,

 

 

 

BWX

 

 

 

 

tCES

tCEH

 

CE

 

 

 

ADV

 

 

 

OE

 

 

 

 

 

 

tCO

A3 A4

tWES tWEH

tDS tDH

A5 A6

Data In (D)

High-Z

t

tOEHZ

 

 

 

 

CLZ

 

Data Out (Q)

High-Z

Q(A1)

Q(A2)

D(A3)

tOELZ

Q(A4) Q(A4+1) Q(A4+2) Q(A4+3)

D(A5) D(A6)

Back-to-Back READs

Single WRITE

BURST READ

DON’T CARE

UNDEFINED

Back-to-Back

WRITEs

Notes:

28.The data bus (Q) remains in high-Z following a Write cycle, unless a new read access is initiated by ADSP or ADSC.

29.GW is HIGH.

Document #: 38-05383 Rev. *E

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Cypress CY7C1442AV33, CY7C1446AV33, CY7C1440AV33 manual Read/Write Cycle Timing26, 28, Clz