Bit Free Running Counter Loading Timing Diagram

CY7C63310, CY7C638xx

Figure 16-4. 16-Bit Free Running Counter Loading Timing Diagram

clk_sys

write

valid

addr

write data

FRT reload ready

Clk Timer

12b Prog Timer

12b reload

interrupt

12-bit programmable timer load timing

Capture timer

clk

16b free running

counter load

	16b free	00A0 00A1 00A2 00A3 00A4 00A5 00A6 00A7 00A8 00A9 00AB 00AC 00AD 00AE 00AF 00B0 00B1 00B2 ACBE ACBF ACC0
	running counter
	running counter

16-bit free running counter loading timing

Figure 16-5. Memory Mapped Registers Read/Write Timing Diagram

clk_sys

rd_wrn

Valid

Addr

rdata

wdata

Document 38-08035 Rev. *K

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Cypress CY7C638xx, CY7C63310 manual Bit Free Running Counter Loading Timing Diagram

CY7C638xx, CY7C63310 specifications

The Cypress CY7C63310 and CY7C638xx series are advanced USB microcontrollers designed for various applications requiring reliable performance and flexibility. These chips are notable for their integration of several key technologies, enabling developers to create innovative electronic designs effortlessly.

The CY7C63310 is a part of the Cypress USB microcontroller family that boasts a fully integrated 8051-compatible microprocessor core. This architecture allows for efficient execution of high-level programming languages like C, enhancing code development efforts. The microcontroller supports USB 2.0 full-speed operation, allowing for high data transfer rates of up to 12 Mbps, essential for applications involving data communication.

One of the standout features of the CY7C63310 is its programmable GPIO (General-Purpose Input/Output) pins, which provide developers with the versatility to configure these pins as inputs, outputs, or alternate functions. This flexibility is particularly advantageous in applications where custom interfaces are essential, such as human-machine interfaces, sensor control, and USB peripherals.

Moreover, the CY7C638xx series presents an even broader array of features. These devices typically support various memory configurations, enabling designers to select from different on-chip RAM and flash memory options. This variety empowers projects requiring a mix of program and data storage capabilities, all while ensuring that performance remains optimal.

Both the CY7C63310 and CY7C638xx series leverage Cypress's EZ-USB technology, which simplifies the process of USB interface implementation. The EZ-USB architecture minimizes the effort associated with USB protocol complexity, allowing developers to focus on the core functionality of their applications.

These microcontrollers also incorporate features such as low-power operation, making them ideal for battery-operated devices. With various power management modes, designers can optimize energy consumption according to the specific needs of their applications.

In terms of connectivity, these chips support multiple interface standards, including SPI, I2C, and UART. These capabilities ensure that developers can easily interface with other components and systems, enhancing the overall utility of the microcontroller.

In summary, the Cypress CY7C63310 and CY7C638xx microcontrollers stand out for their robust features, including integrated USB functionality, flexible GPIO options, and support for various communication protocols. These attributes make them suitable for a wide range of applications, from consumer electronics to industrial automation, making them an excellent choice for developers seeking reliable and adaptable microcontroller solutions.

Contents

Applications FeaturesCypress Semiconductor Corporation 198 Champion Court San Jose, CA Document 38-08035 Rev. *K Revised December 08 Gpio Logic Block Diagram Conventions Introduction Pinouts Die Pad Summary Pad Number Pad Name Microns Gpio Port 1 bit 0/USB D+ 1 If this pin is used as a Pin DescriptionGpio Port 1 bit 1/USB D- 1 If this pin is used as a No connect CPU ArchitectureSupply Ground Flags Register CPU Registers Addressing Modes Source Indexed Opcode Operand Source Direct Opcode Operand10. Destination Direct Opcode Operand Destination Indexed 13. Destination Indexed Source Immediate Opcode Operand 12. Destination Direct Source Immediate Opcode Operand14. Destination Direct Source Direct Opcode Operand 15. Source Indirect Post Increment Opcode Operand Instruction Set Summary Sorted Numerically by Opcode Order2 Instruction Set Summary Flash Program Memory Organization Memory OrganizationPOR/LVD INT0 EP0 EP1 EP2 Flash Data Memory OrganizationSrom Stack begins here and grows upward Srom Function Parameters Variable Name Sram Address Srom Function DescriptionsSrom Return Codes Description ReadBlock Parameters Name Address Description WriteBlock Parameters Name Address Description Protection Modes Settings Description MarketingEraseBlock Parameters Name Address Description Block Block n EraseAll Parameters Name Address Description ProtectBlock Parameters Name Address Description10. Table Read Parameters Name Address Description 11. Return values for Table Read Table Number Return Value Srom Table Checksum Function Clocking12. Checksum Parameters Name Address Description Clock Block Diagram Iosc Trim Iosctr 0x34 R/W Clock Architecture DescriptionBit 40 Gain Lposc Trim Lposctr 0x36 R/W CPU/USB Clock Config Cpuclkcr 0x30 R/WBit 41 Reserved Bit 76 Reserved Bit 5 No Buzz OSC Control 0 OSCCR0 0x1E0 R/W Timer Clock Config Tmrclkcr 0x31 R/W USB Osclock Clock Configuration Osclckcr 0x39 R/WBit 72 Reserved = Tcapclk Timer Capture Clock Tcapclk Interval Timer Clock ItmrclkCou nte r Terru pt Ntro ller Document 38-08035 Rev. *K Clock IO Config Clkiocr 0x32 R/W CPU Clock During Sleep Mode Reset Power on Reset Sleep ModeWatchdog Timer Reset Reset Watchdog Timer Reswdt 0xE3 W Wake up Sequence Sleep Sequence Wake Up Timing Low Power in Sleep Mode Low Voltage Control Register Lvdcr 0x1E3 R/W Low Voltage Detect ControlBit 76 Reserved Bit 54 PORLEV10 Bit 20 VM20 LVD Trip Point V Min Point V Typ Point V Max Bit 72 Reserved Bit 1 LVD Voltage Monitor Comparators Register Vltcmp 0x1E4 RECO Trim Register ECO Ecotr 0x1EB R/W Port Data Registers General Purpose IO Gpio PortsP0 Data Register P0DATA0x00 R/W P2 Data Register P2DATA 0x02 R/W P1 Data Register P1DATA 0x01 R/WP3 Data Register P3DATA 0x03 R/W Gpio Port Configuration P0.1/CLKOUT Configuration P01CR 0x06 R/W P0.0/CLKIN Configuration P00CR 0x05 R/W P0.5/TIO0 P0.6/TIO1 Configuration P05CR-P06CR 0x0A-0x0B R/W P0.2/INT0-P0.4/INT2 Configuration P02CR-P04CR 0x07-0x09 R/W 10. P1.0/D+ Configuration P10CR 0x0D R/W P0.7 Configuration P07CR 0x0C R/W11. P1.1/D- Configuration P11CR 0x0E R/W 12. P1.2 Configuration P12CR 0x0F R/W 14. P1.4-P1.6 Configuration P14CR-P16CR 0x11-0x13 R/W 13. P1.3 Configuration P13CR 0x10 R/W15. P1.7 Configuration P17CR 0x14 R/W 16. P2 Configuration P2CR 0x15 R/W Serial Peripheral Interface SPI 17. P3 Configuration P3CR 0x16 R/WSPI Data Register SPI Data Register Spidata 0x3C R/W SPI Configure Register SPI Mode Timing vs. LSB First, Cpol and Cpha SPI Interface PinsSclk Ssel DAT a Free Running Timer Low order Byte Frtmrl 0x20 R/W Timer RegistersFree Running Timer High-order Byte Frtmrh 0x21 R/W Registers Timer Capture 1 Rising TIO1R 0x23 R/W Timer Capture 0 Rising TIO0R 0x22 R/WTimer Capture 0 Falling TIO0F 0x24 R/W Timer Capture 1 Falling TIO1F 0x25 R/W Bit 74 Reserved Programmable Interval Timer High Pitmrh 0x27 RProgrammable Interval Reload Low Pirl 0x28 R/W 10. Programmable Interval Reload High Pirh 0x29 R/W 11. Timer Configuration Tmrcr 0x2A R/W Timer CaptureBit 20 Reserved 13. Capture Interrupt Status Tcapints 0x2C R/W 12. Capture Interrupt Enable Tcapinte 0x2B R/W Timer Functional Sequence Diagram Bit Free Running Counter Loading Timing Diagram Architectural Description Interrupt Controller Interrupt Trigger Conditions Interrupt ProcessingInterrupt Latency PCH PC158 is cleared to zero Interrupt Clear 0 INTCLR0 0xDA R/W Interrupt RegistersInterrupt Clear 1 INTCLR1 0xDB R/W Interrupt Clear 2 INTCLR2 0xDC R/W Interrupt Mask 3 INTMSK3 0xDE R/W Bit 7 Enable Software Interrupt EnswintBit 60 Reserved Interrupt Mask 2 INTMSK2 0xDF R/W Interrupt Mask 1 INTMSK1 0xE1 R/W Interrupt Vector Clear Register Intvc 0xE2 R/W Interrupt Mask 0 INTMSK0 0xE0 R/W Vreg Control Regulator OutputVreg Control Register Vregcr 0x73 R/W USB Transceiver Configure Register Usbxcr 0x74 R/W USB Transceiver ConfigurationUSB/PS2 Transceiver USB Serial Interface Engine SIE USB Device Address USB DeviceEndpoint 0, 1, and 2 Count USB Device Address Usbcr 0x40 R/W Endpoint 0 Mode EP0MODE 0x44 R/W Endpoint 0 ModeBit 30 Mode Endpoint 1 and 2 Mode EP1MODE EP2MODE 0x45, 0x46 R/W Endpoint 1 and 2 ModeBit 7 Stall Endpoint 0 Data EP0DATA 0x50-0x57 R/W Mode Column USB Mode TablesEncoding Column Endpoint 2 Data EP2DATA 0x60-0x67 R/W SETUP, IN, and OUT Columns Details of Mode for Differing Traffic Conditions Count Fifo Register Summary Addr Name Default Tmrcr Intvc Voltage vs CPU Frequency Characteristics Voltage Vs CPU Frequency Characteristics Absolute Maximum Ratings DC CharacteristicsDetect 3V Regulator General Purpose IO Interface AC CharacteristicsParameter Description Conditions Min Typical Max Unit Clock Cpuclk USB Data Timing Non-USB Mode Driver CharacteristicsSPI Timing Clock Timing Gpio Timing Diagram Differential Data Lines SCK CPOL=0 SCK CPOL=0 SCK CPOL=1 Package Handling Ordering Information Pin 300-Mil Molded DIP P1 Package Diagrams Pin 300-Mil Molded DIP P3 Pin 300-Mil Soic S13 Pin QFN Package Document History Updated part numbers in the header Added block diagrams and timing diagramsRemoved 638xx die diagram and die form pad assignment Removed Gpio port 4 configuration details CMCC/PYRS VGT/AESA Worldwide Sales and Design Support Products PSoC Solutions Sales, Solutions, and Legal InformationUSB