CY7C63310, CY7C638xx

23. Details of Mode for Differing Traffic Conditions (continued)

Control Endpoint

SIE

 

 

Bus Event

 

SIE

EP0 Mode Register

EP0 Count Register

EP0

Interrupt

Comments

Mode

 

Token

Count

Dval

D0/1

Response

S

I

O

A

MODE

DTOG

DVAL

COUNT

FIFO

 

 

1101

 

IN

x

x

x

STALL

 

 

 

 

 

 

 

 

 

 

Stall IN

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

NAK IN

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1100

 

OUT

x

x

x

 

 

 

 

 

 

 

 

 

 

 

Ignore

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1100

 

IN

x

x

x

NAK

 

 

 

 

 

 

 

 

 

If Enabled

NAK IN

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

24. Register Summary

The XIO bit in the CPU Flags Register must be set to access the extended register space for all registers above 0xFF.

Addr

Name

7

6

5

4

3

2

1

0

R/W

Default

00

P0DATA

P0.7

P0.6/TIO1

P0.5/TIO0

P0.4/INT2

P0.3/INT1

P0.2/INT0

P0.1/CLK-

P0.0/CLKI

bbbbbbbb

00000000

 

 

 

 

 

 

 

 

OUT

N

 

 

01

P1DATA

P1.7

P1.6/SMI

P1.5/SMO

P1.4/SCLK

P1.3/SSEL

P1.2/VREG

P1.1/D–

P1.0/D+

bbbbbbbb

00000000

 

 

 

SO

SI

 

 

 

 

 

 

 

02

P2DATA

 

 

 

Res

 

 

P2.1–P2.0

bbbbbbbb

00000000

03

P3DATA

 

 

 

Res

 

 

P3.1–P3.0

bbbbbbbb

00000000

04

P4DATA

 

Res

 

 

Res

 

 

----bbbb

00000000

 

 

 

 

 

 

 

 

 

 

 

 

05

P00CR

Reserved

Int

Int Act

TTL Thresh

Reserved

Open Drain

Pull up

Output

-bbbbbbb

00000000

 

 

 

Enable

Low

 

 

 

Enable

Enable

 

 

06

P01CR

CLK

Int

Int Act

TTL Thresh

Reserved

Open Drain

Pull up

Output

bbbbbbbb

00000000

 

 

Output

Enable

Low

 

 

 

Enable

Enable

 

 

07–09

P02CR–

Reserved

Reserved

Int Act

TTL Thresh

Reserved

Open Drain

Pull up

Output

--bbbbbb

00000000

 

P04CR

 

 

Low

 

 

 

Enable

Enable

 

 

0A–0B

P05CR–

TIO

Int

Int Act

TTL Thresh

Reserved

Open Drain

Pull up

Output

bbbbbbbb

00000000

 

P06CR

Output

Enable

Low

 

 

 

Enable

Enable

 

 

0C

P07CR

Reserved

Int

Int Act

TTL Thresh

Reserved

Open Drain

Pull up

Output

-bbbbbbb

00000000

 

 

 

Enable

Low

 

 

 

Enable

Enable

 

 

0D

P10CR

Reserved

Int

Int Act

 

Reserved

 

PS/2 Pull

Output

-bb---bb

00000000

 

 

 

Enable

Low

 

 

 

up Enable

Enable

 

 

0E

P11CR

Reserved

Int

Int Act

Reserved

Open Drain

Reserved

Output

-bb--b-b

00000000

 

 

 

Enable

Low

 

 

 

 

Enable

 

 

0F

P12CR

CLK

Int

Int Act

TTL Thresh

Reserved

Open Drain

Pull up

Output

bbbbbbbb

00000000

 

 

Output

Enable

Low

 

 

 

Enable

Enable

 

 

10

P13CR

Reserved

Int

Int Act

3.3V Drive

High Sink

Open Drain

Pull up

Output

-bbbbbbb

00000000

 

 

 

Enable

Low

 

 

 

Enable

Enable

 

 

11–13

P14CR–

SPI Use

Int

Int Act

3.3V Drive

High Sink

Open Drain

Pull up

Output

bbbbbbbb

00000000

 

P16CR

 

Enable

Low

 

 

 

Enable

Enable

 

 

14

P17CR

Reserved

Int

Int Act

TTL Thresh

High Sink

Open Drain

Pull up

Output

-bbbbbbb

00000000

 

 

 

Enable

Low

 

 

 

Enable

Enable

 

 

15

P2CR

Reserved

Int

Int Act

TTL Thresh

Reserved

Open Drain

Pull up

Output

-bbbbbbb

00000000

 

 

 

Enable

Low

 

 

 

Enable

Enable

 

 

16

P3CR

Reserved

Int

Int Act

TTL Thresh

Reserved

Open Drain

Pull up

Output

-bbbbbbb

00000000

 

 

 

Enable

Low

 

 

 

Enable

Enable

 

 

20

FRTMRL

 

 

 

Free Running Timer [7:0]

 

 

bbbbbbbb

00000000

 

 

 

 

 

 

 

 

 

 

21

FRTMRH

 

 

 

Free Running Timer [15:8]

 

 

bbbbbbbb

00000000

 

 

 

 

 

 

 

 

 

 

 

22

TCAP0R

 

 

 

Capture 0 Rising [7:0]

 

 

 

bbbbbbbb

00000000

 

 

 

 

 

 

 

 

 

 

 

23

TCAP1R

 

 

 

Capture 1 Rising [7:0]

 

 

 

bbbbbbbb

00000000

 

 

 

 

 

 

 

 

 

 

 

24

TCAP0F

 

 

 

Capture 0 Falling [7:0]

 

 

 

bbbbbbbb

00000000

 

 

 

 

 

 

 

 

 

 

 

25

TCAP1F

 

 

 

Capture 1 Falling [7:0]

 

 

 

bbbbbbbb

00000000

 

 

 

 

 

 

 

 

 

 

26

PITMRL

 

 

 

Prog Interval Timer [7:0]

 

 

bbbbbbbb

00000000

 

 

 

 

 

 

 

 

 

 

 

27

PITMRH

 

Reserved

 

 

Prog Interval Timer [11:8]

 

----bbbb

00000000

 

 

 

 

 

 

 

 

 

 

 

 

28

PIRL

 

 

 

Prog Interval [7:0]

 

 

 

bbbbbbbb

00000000

 

 

 

 

 

 

 

 

 

 

 

29

PIRH

 

Reserved

 

 

Prog Interval [11:8]

 

----bbbb

00000000

 

 

 

 

 

 

 

 

 

 

 

 

Document 38-08035 Rev. *K

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Cypress CY7C63310, CY7C638xx manual Register Summary, Addr Name Default

CY7C638xx, CY7C63310 specifications

The Cypress CY7C63310 and CY7C638xx series are advanced USB microcontrollers designed for various applications requiring reliable performance and flexibility. These chips are notable for their integration of several key technologies, enabling developers to create innovative electronic designs effortlessly.

The CY7C63310 is a part of the Cypress USB microcontroller family that boasts a fully integrated 8051-compatible microprocessor core. This architecture allows for efficient execution of high-level programming languages like C, enhancing code development efforts. The microcontroller supports USB 2.0 full-speed operation, allowing for high data transfer rates of up to 12 Mbps, essential for applications involving data communication.

One of the standout features of the CY7C63310 is its programmable GPIO (General-Purpose Input/Output) pins, which provide developers with the versatility to configure these pins as inputs, outputs, or alternate functions. This flexibility is particularly advantageous in applications where custom interfaces are essential, such as human-machine interfaces, sensor control, and USB peripherals.

Moreover, the CY7C638xx series presents an even broader array of features. These devices typically support various memory configurations, enabling designers to select from different on-chip RAM and flash memory options. This variety empowers projects requiring a mix of program and data storage capabilities, all while ensuring that performance remains optimal.

Both the CY7C63310 and CY7C638xx series leverage Cypress's EZ-USB technology, which simplifies the process of USB interface implementation. The EZ-USB architecture minimizes the effort associated with USB protocol complexity, allowing developers to focus on the core functionality of their applications.

These microcontrollers also incorporate features such as low-power operation, making them ideal for battery-operated devices. With various power management modes, designers can optimize energy consumption according to the specific needs of their applications.

In terms of connectivity, these chips support multiple interface standards, including SPI, I2C, and UART. These capabilities ensure that developers can easily interface with other components and systems, enhancing the overall utility of the microcontroller.

In summary, the Cypress CY7C63310 and CY7C638xx microcontrollers stand out for their robust features, including integrated USB functionality, flexible GPIO options, and support for various communication protocols. These attributes make them suitable for a wide range of applications, from consumer electronics to industrial automation, making them an excellent choice for developers seeking reliable and adaptable microcontroller solutions.