Cypress CY7C63310, CY7C638xx USB Data Timing, Non-USB Mode Driver Characteristics, SPI Timing

CY7C63310, CY7C638xx

28. AC Characteristics (continued)

Parameter	Description		Conditions		Min	Typical	Max	Unit
USB Driver
TR1	Transition Rise Time	CLOAD = 200 pF			75			ns
TR2	Transition Rise Time	CLOAD = 600 pF					300	ns
TF1	Transition Fall Time	CLOAD = 200 pF			75			ns
TF2	Transition Fall Time	CLOAD = 600 pF					300	ns
TR	Rise/Fall Time Matching				80		125	%
VCRS	Output Signal Crossover Voltage				1.3		2.0	V
USB Data	Timing
TDRATE	Low Speed Data Rate	Average Bit Rate (1.5 Mbps ± 1.5%)			1.4775		1.5225	Mbps
TDJR1	Receiver Data Jitter Tolerance	To next transition			–75		75	ns
TDJR2	Receiver Data Jitter Tolerance	To pair transition			–45		45	ns
TDEOP	Differential to EOP Transition Skew				–40		100	ns
TEOPR1	EOP Width at Receiver	Rejects as EOP					330	ns
TEOPR2	EOP Width at Receiver	Accept as EOP			675			ns
TEOPT	Source EOP Width				1.25		1.5	μs
TUDJ1	Differential Driver Jitter	To next transition			–95		95	ns
TUDJ2	Differential Driver Jitter	To pair transition			–95		95	ns
TLST	Width of SE0 during Diff. Transition						210	ns
Non-USB	Mode Driver Characteristics
TFPS2	SDATA/SCK Transition Fall Time				50		300	ns
GPIO Timing
TR_GPIO	Output Rise Time[8]	Measured between 10 and 90%					50	ns
		Vdd/Vreg with 50 pF load
TF_GPIO	Output Fall Time[8]	Measured between 10 and 90%					15	ns
		Vdd/Vreg with 50 pF load
SPI Timing
TSMCK	SPI Master Clock Rate	FCPUCLK/6					2	MHz
TSSCK	SPI Slave Clock Rate						2.2	MHz
TSCKH	SPI Clock High Time	High for CPOL = 0, Low for CPOL = 1			125			ns
TSCKL	SPI Clock Low Time	Low for CPOL = 0, High for CPOL = 1			125			ns
T	Master Data Output Time[10]	SCK to data valid			–25		50	ns
MDO
TMDO1	Master Data Output Time,	Time before leading SCK edge			100			ns
	First bit with CPHA = 0
TMSU	Master Input Data Setup time				50			ns
TMHD	Master Input Data Hold time				50			ns
TSSU	Slave Input Data Setup Time				50			ns
TSHD	Slave Input Data Hold Time				50			ns
TSDO	Slave Data Output Time	SCK to data valid					100	ns
TSDO1	Slave Data Output Time,	Time after	SS	LOW to data valid			100	ns
	First bit with CPHA = 0
TSSS	Slave Select Setup Time	Before first SCK edge			150			ns
TSSH	Slave Select Hold Time	After last SCK edge			150			ns

Note

10. In Master mode, first bit is available 0.5 SPICLK cycle before Master clock edge available on the SCLK pin.

Document 38-08035 Rev. *K Page 70 of 83

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