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Cypress CY7C63310, CY7C638xx USB Data Timing, Non-USB Mode Driver Characteristics, SPI Timing

Models: CY7C638xx CY7C63310

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CY7C63310, CY7C638xx

28. AC Characteristics (continued)

Parameter	Description		Conditions		Min	Typical	Max	Unit
USB Driver

TR1	Transition Rise Time	CLOAD = 200 pF			75			ns
TR2	Transition Rise Time	CLOAD = 600 pF					300	ns
TF1	Transition Fall Time	CLOAD = 200 pF			75			ns
TF2	Transition Fall Time	CLOAD = 600 pF					300	ns
TR	Rise/Fall Time Matching				80		125	%
VCRS	Output Signal Crossover Voltage				1.3		2.0	V
USB Data	Timing
TDRATE	Low Speed Data Rate	Average Bit Rate (1.5 Mbps ± 1.5%)			1.4775		1.5225	Mbps
TDJR1	Receiver Data Jitter Tolerance	To next transition			–75		75	ns
TDJR2	Receiver Data Jitter Tolerance	To pair transition			–45		45	ns
TDEOP	Differential to EOP Transition Skew				–40		100	ns
TEOPR1	EOP Width at Receiver	Rejects as EOP					330	ns
TEOPR2	EOP Width at Receiver	Accept as EOP			675			ns
TEOPT	Source EOP Width				1.25		1.5	μs
TUDJ1	Differential Driver Jitter	To next transition			–95		95	ns
TUDJ2	Differential Driver Jitter	To pair transition			–95		95	ns
TLST	Width of SE0 during Diff. Transition						210	ns
Non-USB	Mode Driver Characteristics

TFPS2	SDATA/SCK Transition Fall Time				50		300	ns
GPIO Timing

TR_GPIO	Output Rise Time[8]	Measured between 10 and 90%					50	ns
		Vdd/Vreg with 50 pF load
TF_GPIO	Output Fall Time[8]	Measured between 10 and 90%					15	ns
		Vdd/Vreg with 50 pF load
SPI Timing

TSMCK	SPI Master Clock Rate	FCPUCLK/6					2	MHz
TSSCK	SPI Slave Clock Rate						2.2	MHz
TSCKH	SPI Clock High Time	High for CPOL = 0, Low for CPOL = 1			125			ns
TSCKL	SPI Clock Low Time	Low for CPOL = 0, High for CPOL = 1			125			ns
T	Master Data Output Time[10]	SCK to data valid			–25		50	ns
MDO
TMDO1	Master Data Output Time,	Time before leading SCK edge			100			ns
	First bit with CPHA = 0
TMSU	Master Input Data Setup time				50			ns
TMHD	Master Input Data Hold time				50			ns
TSSU	Slave Input Data Setup Time				50			ns
TSHD	Slave Input Data Hold Time				50			ns
TSDO	Slave Data Output Time	SCK to data valid					100	ns
TSDO1	Slave Data Output Time,	Time after	SS	LOW to data valid			100	ns
	First bit with CPHA = 0
TSSS	Slave Select Setup Time	Before first SCK edge			150			ns
TSSH	Slave Select Hold Time	After last SCK edge			150			ns

Note

10. In Master mode, first bit is available 0.5 SPICLK cycle before Master clock edge available on the SCLK pin.

Document 38-08035 Rev. *K

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Cypress CY7C63310, CY7C638xx manual USB Data Timing, Non-USB Mode Driver Characteristics, SPI Timing

Contents

Cypress Semiconductor Corporation 198 Champion Court FeaturesApplications San Jose, CA Document 38-08035 Rev. *K Revised December 08Logic Block Diagram M8C CPUIntroduction ConventionsPinouts Die Pad Summary Pad Number Pad Name Microns Gpio Port 1 bit 0/USB D+ 1 If this pin is used as a Pin DescriptionGpio Port 1 bit 1/USB D- 1 If this pin is used as a Supply CPU ArchitectureNo connect GroundCPU Registers Flags RegisterAddressing Modes 10. Destination Direct Opcode Operand Source Direct Opcode OperandSource Indexed Opcode Operand Destination Indexed14. Destination Direct Source Direct Opcode Operand 12. Destination Direct Source Immediate Opcode Operand13. Destination Indexed Source Immediate Opcode Operand 15. Source Indirect Post Increment Opcode OperandInstruction Set Summary Instruction Set Summary Sorted Numerically by Opcode Order2POR/LVD INT0 Memory OrganizationFlash Program Memory Organization EP0 EP1 EP2Srom Data Memory OrganizationFlash Stack begins here and grows upwardSrom Return Codes Description Srom Function DescriptionsSrom Function Parameters Variable Name Sram Address ReadBlock Parameters Name Address DescriptionEraseBlock Parameters Name Address Description Protection Modes Settings Description MarketingWriteBlock Parameters Name Address Description Block Block n10. Table Read Parameters Name Address Description ProtectBlock Parameters Name Address DescriptionEraseAll Parameters Name Address Description 11. Return values for Table Read Table Number Return ValueSrom Table Checksum Function Clocking12. Checksum Parameters Name Address Description Clock Block Diagram Iosc Trim Iosctr 0x34 R/W Clock Architecture DescriptionBit 40 Gain Lposc Trim Lposctr 0x36 R/W CPU/USB Clock Config Cpuclkcr 0x30 R/WBit 41 Reserved OSC Control 0 OSCCR0 0x1E0 R/W Bit 76 Reserved Bit 5 No BuzzBit 72 Reserved USB Osclock Clock Configuration Osclckcr 0x39 R/WTimer Clock Config Tmrclkcr 0x31 R/W = TcapclkTimer Capture Clock Tcapclk Interval Timer Clock ItmrclkCou nte r Terru pt Ntro ller Document 38-08035 Rev. *K CPU Clock During Sleep Mode Clock IO Config Clkiocr 0x32 R/WReset Watchdog Timer Reset Sleep ModePower on Reset Reset Watchdog Timer Reswdt 0xE3 WSleep Sequence Wake up SequenceLow Power in Sleep Mode Wake Up TimingBit 76 Reserved Bit 54 PORLEV10 Low Voltage Detect ControlLow Voltage Control Register Lvdcr 0x1E3 R/W Bit 20 VM20 LVD Trip Point V Min Point V Typ Point V MaxECO Trim Register Voltage Monitor Comparators Register Vltcmp 0x1E4 RBit 72 Reserved Bit 1 LVD ECO Ecotr 0x1EB R/WPort Data Registers General Purpose IO Gpio PortsP0 Data Register P0DATA0x00 R/W P2 Data Register P2DATA 0x02 R/W P1 Data Register P1DATA 0x01 R/WP3 Data Register P3DATA 0x03 R/W Gpio Port Configuration P0.0/CLKIN Configuration P00CR 0x05 R/W P0.1/CLKOUT Configuration P01CR 0x06 R/WP0.2/INT0-P0.4/INT2 Configuration P02CR-P04CR 0x07-0x09 R/W P0.5/TIO0 P0.6/TIO1 Configuration P05CR-P06CR 0x0A-0x0B R/W11. P1.1/D- Configuration P11CR 0x0E R/W P0.7 Configuration P07CR 0x0C R/W10. P1.0/D+ Configuration P10CR 0x0D R/W 12. P1.2 Configuration P12CR 0x0F R/W15. P1.7 Configuration P17CR 0x14 R/W 13. P1.3 Configuration P13CR 0x10 R/W14. P1.4-P1.6 Configuration P14CR-P16CR 0x11-0x13 R/W 16. P2 Configuration P2CR 0x15 R/WSPI Data Register 17. P3 Configuration P3CR 0x16 R/WSerial Peripheral Interface SPI SPI Data Register Spidata 0x3C R/WSPI Configure Register SPI Mode Timing vs. LSB First, Cpol and Cpha SPI Interface PinsSclk Ssel DAT a Free Running Timer High-order Byte Frtmrh 0x21 R/W Timer RegistersFree Running Timer Low order Byte Frtmrl 0x20 R/W RegistersTimer Capture 0 Falling TIO0F 0x24 R/W Timer Capture 0 Rising TIO0R 0x22 R/WTimer Capture 1 Rising TIO1R 0x23 R/W Timer Capture 1 Falling TIO1F 0x25 R/WProgrammable Interval Reload Low Pirl 0x28 R/W Programmable Interval Timer High Pitmrh 0x27 RBit 74 Reserved 10. Programmable Interval Reload High Pirh 0x29 R/W11. Timer Configuration Tmrcr 0x2A R/W Timer CaptureBit 20 Reserved 12. Capture Interrupt Enable Tcapinte 0x2B R/W 13. Capture Interrupt Status Tcapints 0x2C R/WTimer Functional Sequence Diagram Bit Free Running Counter Loading Timing Diagram Interrupt Controller Architectural DescriptionInterrupt Latency Interrupt ProcessingInterrupt Trigger Conditions PCH PC158 is cleared to zeroInterrupt Clear 1 INTCLR1 0xDB R/W Interrupt RegistersInterrupt Clear 0 INTCLR0 0xDA R/W Interrupt Clear 2 INTCLR2 0xDC R/WInterrupt Mask 3 INTMSK3 0xDE R/W Bit 7 Enable Software Interrupt EnswintBit 60 Reserved Interrupt Mask 2 INTMSK2 0xDF R/W Interrupt Mask 1 INTMSK1 0xE1 R/W Interrupt Mask 0 INTMSK0 0xE0 R/W Interrupt Vector Clear Register Intvc 0xE2 R/WVreg Control Regulator OutputVreg Control Register Vregcr 0x73 R/W USB/PS2 Transceiver USB Transceiver ConfigurationUSB Transceiver Configure Register Usbxcr 0x74 R/W USB Serial Interface Engine SIEEndpoint 0, 1, and 2 Count USB DeviceUSB Device Address USB Device Address Usbcr 0x40 R/WEndpoint 0 Mode EP0MODE 0x44 R/W Endpoint 0 ModeBit 30 Mode Bit 7 Stall Endpoint 1 and 2 ModeEndpoint 1 and 2 Mode EP1MODE EP2MODE 0x45, 0x46 R/W Endpoint 0 Data EP0DATA 0x50-0x57 R/WEncoding Column USB Mode TablesMode Column Endpoint 2 Data EP2DATA 0x60-0x67 R/WDetails of Mode for Differing Traffic Conditions SETUP, IN, and OUT ColumnsCount Fifo Addr Name Default Register SummaryTmrcr Intvc Voltage Vs CPU Frequency Characteristics Voltage vs CPU Frequency CharacteristicsDetect DC CharacteristicsAbsolute Maximum Ratings 3V RegulatorParameter Description Conditions Min Typical Max Unit Clock AC CharacteristicsGeneral Purpose IO Interface CpuclkUSB Data Timing Non-USB Mode Driver CharacteristicsSPI Timing Gpio Timing Diagram Clock TimingDifferential Data Lines SCK CPOL=0 SCK CPOL=0 SCK CPOL=1 Ordering Information Package HandlingPackage Diagrams Pin 300-Mil Molded DIP P1Pin 300-Mil Molded DIP P3 Pin 300-Mil Soic S13 Pin QFN Package Document History Removed 638xx die diagram and die form pad assignment Added block diagrams and timing diagramsUpdated part numbers in the header Removed Gpio port 4 configuration detailsVGT/AESA CMCC/PYRSWorldwide Sales and Design Support Products PSoC Solutions Sales, Solutions, and Legal InformationUSB