Cypress CY7C63310, CY7C638xx manual Sleep Mode, Power on Reset, Watchdog Timer Reset

CY7C63310, CY7C638xx

11.1 Power on Reset

POR occurs every time the power to the device is switched on. POR is released when the supply is typically 2.6V for the upward supply transition, with typically 50 mV of hysteresis during the power on transient. Bit 4 of the System Status and Control Register (CPU_SCR) is set to record this event (the register contents are set to 00010000 by the POR). After a POR, the microprocessor is held off for approximately 20 ms for the VCC supply to stabilize before executing the first instruction at address 0x00 in the Flash. If the VCC voltage drops below the POR downward supply trip point, POR is reasserted. The VCC supply must ramp linearly from 0 to 4V in less than 200 ms.

Note The PORS status bit is set at POR and is cleared only by the user. It cannot be set by firmware.

11.2 Watchdog Timer Reset

The user has the option to enable the WDT. The WDT is enabled by clearing the PORS bit. After the PORS bit is cleared, the WDT cannot be disabled. The only exception to this is if a POR event takes place, which disables the WDT.

Table 11-2. Reset Watchdog Timer (RESWDT) [0xE3] [W]

The sleep timer is used to generate the sleep time period and the Watchdog time period. The sleep timer uses the Internal 32 kHz Low power Oscillator system clock to produce the sleep time period. The user can program the sleep time period using the Sleep Timer bits of the OSC_CR0 Register (Table 10-4on page 23). When the sleep time elapses (sleep timer overflows), an interrupt to the Sleep Timer Interrupt Vector is generated.

The Watchdog Timer period is automatically set to be three counts of the Sleep Timer overflow. This represents between two and three sleep intervals depending on the count in the Sleep Timer at the previous WDT clear. When this timer reaches three, a WDR is generated.

The user can either clear the WDT, or the WDT and the Sleep Timer. When the user writes to the Reset WDT Register (RES_WDT), the WDT is cleared. If the data that is written is the hex value 0x38, the Sleep Timer is also cleared at the same time.

Bit #	7	6	5	4	3	2	1	0
Field				Reset Watchdog Timer [7:0]
Read/Write	W	W	W	W	W	W	W	W
Default	0	0	0	0	0	0	0	0

Any write to this register clears Watchdog Timer; a write of 0x38 also clears the Sleep Timer.

Bit [7:0]: Reset Watchdog Timer [7:0]

12. Sleep Mode

The CPU is put to sleep only by the firmware. This is accomplished by setting the Sleep bit in the System Status and Control Register (CPU_SCR). This stops the CPU from executing instructions, and the CPU remains asleep until an interrupt comes pending, or there is a reset event (either a Power on Reset, or a Watchdog Timer Reset).

The Low Voltage Detection circuit (LVD) drops into fully functional power reduced states, and the latency for the LVD is increased. The actual latency is traded against power consumption by changing Sleep Duty Cycle field of the ECO_TR Register.

The Internal 32 kHz Low speed Oscillator remains running. Before entering the suspend mode, the firmware can optionally configure the 32 kHz Low speed Oscillator to operate in a low power mode to help reduce the over all power consumption (Using Bit 7, Table 10-2on page 22). This helps save approximately 5 μA; however, the trade off is that the 32 kHz Low speed Oscillator is less accurate.

All interrupts remain active. Only the occurrence of an interrupt wakes the part from sleep. The Stop bit in the System Status and Control Register (CPU_SCR) must be cleared for a part to resume out of sleep. The Global Interrupt Enable bit of the CPU Flags Register (CPU_F) does not have any effect. Any unmasked interrupt wakes the system up. As a result, any interrupts not intended for waking must be disabled through the Interrupt Mask Registers.

When the CPU enters sleep mode the CPUCLK Select (Bit 1, Table 10-3on page 22) is forced to the Internal Oscillator. The internal oscillator recovery time is three clock cycles of the Internal 32 kHz Low power Oscillator. The Internal 24 MHz Oscillator restarts immediately on exiting Sleep mode. If an external clock is used, firmware switches the clock source for the CPU.

On exiting sleep mode, after the clock is stable and the delay time has expired, the instruction immediately following the sleep instruction is executed before the interrupt service routine (if enabled).

The Sleep interrupt allows the microcontroller to wake up periodically and poll system components while maintaining very low average power consumption. The Sleep interrupt may also be used to provide periodic interrupts during non-sleep modes.

Document 38-08035 Rev. *K Page 28 of 83

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