Cypress CY7C638xx, CY7C63310 manual Tmrcr

CY7C63310, CY7C638xx

24. Register Summary (continued)

The XIO bit in the CPU Flags Register must be set to access the extended register space for all registers above 0xFF.

Addr	Name	7	6	5	4	3	2	1	0	R/W	Default
2A	TMRCR	First Edge	8-bit capture Prescale			Cap0 16bit		Reserved		bbbbb---	00000000
		Hold				Enable
2B	TCAPINTE		Reserved			Cap1 Fall	Cap1 Rise	Cap0 Fall	Cap0 Rise	----bbbb	00000000
						Active	Active	Active	Active
2C	TCAPINTS		Reserved			Cap1 Fall	Cap1 Rise	Cap0 Fall	Cap0 Rise	----bbbb	00000000
						Active	Active	Active	Active
30	CPUCLKCR	Reserved	USB	USB CLK		Reserved			CPU	-bb----b	00010000
			CLK/2	Select					CLK Select
			Disable
31	ITMRCLKCR	TCAPCLK Divider		TCAPCLK Select		ITMRCLK Divider		ITMRCLK Select		bbbbbbbb	10001111
32	CLKIOCR		Reserved			Reserved		CLKOUT Select		---bbbbb	00000000
34	IOSCTR		foffset[2:0]				Gain[4:0]			bbbbbbbb	000ddddd
36	LPOSCTR	32 kHz	Reserved	32 kHz Bias Trim [1:0]			32 kHz Freq Trim [3:0]			b-bbbbbb	dddddddd
		Low
		Power
39	OSCLCKCR			Reserved				Fine Tune	USB	------bb	00000000
								Only	Osclock
									Disable
3C	SPIDATA				SPIData[7:0]					bbbbbbbb	00000000
3D	SPICR	Swap	LSB First	Comm Mode		CPOL	CPHA	SCLK Select		bbbbbbbb	00000000
40	USBCR	USB			Device Address[6:0]					bbbbbbbb	00000000
		Enable
41	EP0CNT	Data	Data Valid	Reserved			Byte Count[3:0]			bbbbbbbb	00000000
		Toggle
42	EP1CNT	Data	Data Valid	Reserved			Byte Count[3:0]			bbbbbbbb	00000000
		Toggle
43	EP2CNT	Data	Data Valid	Reserved			Byte Count[3:0]			bbbbbbbb	00000000
		Toggle
44	EP0MODE	Setup	IN rcv’d	OUT rcv’d	ACK’d trans		Mode[3:0]			ccccbbbb	00000000
		rcv’d
45	EP1MODE	Stall	Reserved	NAK Int	Ack’d trans		Mode[3:0]			b-bcbbbb	00000000
				Enable
46	EP2MODE	Stall	Reserved	NAK Int	Ack’d trans		Mode[3:0]			b-bcbbbb	00000000
				Enable
50–57	EP0DATA				Endpoint 0 Data Buffer [7:0]					bbbbbbbb	????????
58–5F	EP1DATA				Endpoint 1 Data Buffer [7:0]					bbbbbbbb	????????
60–67	EP2DATA				Endpoint 2 Data Buffer [7:0]					bbbbbbbb	????????
73	VREGCR			Reserved				Keep Alive	VREG	------bb	00000000
									Enable
74	USBXCR	USB Pull			Reserved				USB Force	b------b	00000000
		up Enable							State
DA	INT_CLR0	GPIO Port	Sleep	INT1	GPIO Port	SPI	SPI Transmit	INT0	POR/LVD	bbbbbbbb	00000000
		1	Timer		0	Receive
DB	INT_CLR1	TCAP0	Prog	1-ms	USB Active	USB Reset	USB EP2	USB EP1	USB EP0	bbbbbbbb	00000000
			Interval	Timer
			Timer
DC	INT_CLR2	Reserved	Reserved	GPIO Port	GPIO Port 2	PS/2 Data	INT2	16-bit	TCAP1	-bbbbbbb	00000000
				3		Low		Counter
								Wrap
DE	INT_MSK3	ENSWINT				Reserved				b-------	00000000
DF	INT_MSK2	Reserved	Reserved	GPIO Port	GPIO Port 2	PS/2 Data	INT2	16-bit	TCAP1	-bbbbbbb	00000000
				3	Int Enable	Low Int	Int Enable	Counter	Int Enable
				Int Enable		Enable		Wrap
								Int Enable
E1	INT_MSK1	TCAP0	Prog	1-ms	USB Active	USB Reset	USB EP2	USB EP1	USB EP0	bbbbbbbb	00000000
		Int Enable	Interval	Timer	Int Enable	Int Enable	Int Enable	Int Enable	Int Enable
			Timer	Int Enable
			Int Enable
E0	INT_MSK0	GPIO Port	Sleep	INT1	GPIO Port 0	SPI	SPI Transmit	INT0	POR/LVD	bbbbbbbb	00000000
		1	Timer	Int Enable	Int Enable	Receive	Int Enable	Int Enable	Int Enable
		Int Enable	Int Enable			Int Enable

Document 38-08035 Rev. *K Page 65 of 83

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