Cypress CY7C63310, CY7C638xx Absolute Maximum Ratings, DC Characteristics, Detect, 3V Regulator

CY7C63310, CY7C638xx

26. Absolute Maximum Ratings

Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested.

Storage Temperature		–40°C to +90°C
Ambient Temperature with Power Applied		..... –0°C to +70°C
Supply Voltage on VCC Relative to VSS		–0.5V to +7.0V
DC Input Voltage	–0.5V to + VCC + 0.5V
DC Voltage Applied to Outputs in
High-Z State	–0.5V to + VCC + 0.5V

Maximum Total Sink Current into Port 0
and Port 1 pins	70 mA

Maximum Total Source Output Current into GPIO Pins30 mA

Maximum On-chip Power Dissipation
on any GPIO Pin	50 mW
Power Dissipation	300 mW
Static Discharge Voltage	2200V
Latch Up Current	200 mA

27. DC Characteristics

Parameter	Description	Conditions	Min	Typical	Max	Unit
	General
VCC1	Operating Voltage	No USB activity, CPU speed < 12 MHz	4.0		5.5	V
VCC2	Operating Voltage	USB activity, CPU speed < 12 MHz	4.35		5.25	V
VCC3	Operating Voltage	Flash programming	4.0		5.5	V
VCC4	Operating Voltage	No USB activity, CPU speed is	4.75		5.5	V
		between 12 MHz and 24 MHz
TFP	Operating Temp	Flash Programming	0		70	°C
ICC1	VCC Operating Supply Current	VCC = 5.25V, no GPIO loading,			40	mA
		24 MHz
ICC2	VCC Operating Supply Current	VCC = 5.0V, no GPIO loading, 6 MHz		10		mA
ISB1	Standby Current	Internal and External Oscillators,			10	μA
		Bandgap, Flash, CPU Clock, Timer
		Clock, USB Clock all disabled
Low Voltage	Detect
VLVD	Low-Voltage Detect Trip Voltage		2.681		4.872	V
	(8 programmable trip points)
3.3V Regulator
IVREG	Max Regulator Output Current	4.35V < VCC < 5.5V			125	mA
IKA	Keep Alive Current	When regulator is disabled with			20	μA
		“keep alive” enable
VKA	Keep Alive Voltage	Keep alive bit set in VREGCR	2.35		3.8	V
VREG1	VREG Output Voltage	VCC > 4.35V, 0 < temp < 40°C,	3.0		3.6	V
		25 mA < IVREG < 125 mA (3.3V ± 8%)
		T = 0 to 70C
VREG2	VREG Output Voltage	VCC > 4.35V, 0 < temp < 40°C,	3.15		3.45	V
		1 mA < IVREG < 25 mA (3.3V ± 4%)
		T = 0 to 40°C
CLOAD	Capacitive load on Vreg pin		1		2	μF
LNREG	Line Regulation				1	%/V
LDREG	Load Regulation				0.04	%/mA
USB Interface
VON	Static Output High	15K ± 5% Ohm to VSS	2.8		3.6	V
VOFF	Static Output Low	RUP is enabled			0.3	V

Note

6. In Master mode, first bit is available 0.5 SPICLK cycle before Master clock edge available on the SCLK pin.

Document 38-08035 Rev. *K Page 68 of 83

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