Clock Timing, Gpio Timing Diagram | Cypress CY7C638xx, CY7C63310

CY7C63310, CY7C638xx

Figure 28-1. Clock Timing

			TCYC
		TCH
CLOCK
			TCL
		Figure 28-2. GPIO Timing Diagram
90%
GPIO Pin Output
Voltage
10%
		TR_GPIO	TF_GPIO
		Figure 28-3. USB Data Signal Timing
Voh D	+	TR	TF
Voh D		90%	90%
Vcrs		90%	90%
Vcrs		10%
Vol		10%	10%
Vol
D−

TPERIOD

Differential Data Lines

Figure 28-4. Receiver Jitter Tolerance

TJR

TJR1

Consecutive

Transitions

N* TPERIOD + TJR1

Paired

Transitions

N * TPERIOD + TJR2

TJR2

Document 38-08035 Rev. *K

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Cypress CY7C638xx, CY7C63310 manual Clock Timing, Gpio Timing Diagram

CY7C638xx, CY7C63310 specifications

The Cypress CY7C63310 and CY7C638xx series are advanced USB microcontrollers designed for various applications requiring reliable performance and flexibility. These chips are notable for their integration of several key technologies, enabling developers to create innovative electronic designs effortlessly.

The CY7C63310 is a part of the Cypress USB microcontroller family that boasts a fully integrated 8051-compatible microprocessor core. This architecture allows for efficient execution of high-level programming languages like C, enhancing code development efforts. The microcontroller supports USB 2.0 full-speed operation, allowing for high data transfer rates of up to 12 Mbps, essential for applications involving data communication.

One of the standout features of the CY7C63310 is its programmable GPIO (General-Purpose Input/Output) pins, which provide developers with the versatility to configure these pins as inputs, outputs, or alternate functions. This flexibility is particularly advantageous in applications where custom interfaces are essential, such as human-machine interfaces, sensor control, and USB peripherals.

Moreover, the CY7C638xx series presents an even broader array of features. These devices typically support various memory configurations, enabling designers to select from different on-chip RAM and flash memory options. This variety empowers projects requiring a mix of program and data storage capabilities, all while ensuring that performance remains optimal.

Both the CY7C63310 and CY7C638xx series leverage Cypress's EZ-USB technology, which simplifies the process of USB interface implementation. The EZ-USB architecture minimizes the effort associated with USB protocol complexity, allowing developers to focus on the core functionality of their applications.

These microcontrollers also incorporate features such as low-power operation, making them ideal for battery-operated devices. With various power management modes, designers can optimize energy consumption according to the specific needs of their applications.

In terms of connectivity, these chips support multiple interface standards, including SPI, I2C, and UART. These capabilities ensure that developers can easily interface with other components and systems, enhancing the overall utility of the microcontroller.

In summary, the Cypress CY7C63310 and CY7C638xx microcontrollers stand out for their robust features, including integrated USB functionality, flexible GPIO options, and support for various communication protocols. These attributes make them suitable for a wide range of applications, from consumer electronics to industrial automation, making them an excellent choice for developers seeking reliable and adaptable microcontroller solutions.

Contents

San Jose, CA Document 38-08035 Rev. *K Revised December 08 FeaturesApplications Cypress Semiconductor Corporation 198 Champion Court Gpio Logic Block Diagram Conventions Introduction Pinouts Die Pad Summary Pad Number Pad Name Microns Gpio Port 1 bit 1/USB D- 1 If this pin is used as a Pin DescriptionGpio Port 1 bit 0/USB D+ 1 If this pin is used as a Ground CPU ArchitectureNo connect Supply Flags Register CPU Registers Addressing Modes Destination Indexed Source Direct Opcode OperandSource Indexed Opcode Operand 10. Destination Direct Opcode Operand 15. Source Indirect Post Increment Opcode Operand 12. Destination Direct Source Immediate Opcode Operand13. Destination Indexed Source Immediate Opcode Operand 14. Destination Direct Source Direct Opcode Operand Instruction Set Summary Sorted Numerically by Opcode Order2 Instruction Set Summary EP0 EP1 EP2 Memory OrganizationFlash Program Memory Organization POR/LVD INT0 Stack begins here and grows upward Data Memory OrganizationFlash Srom ReadBlock Parameters Name Address Description Srom Function DescriptionsSrom Function Parameters Variable Name Sram Address Srom Return Codes Description Block Block n Protection Modes Settings Description MarketingWriteBlock Parameters Name Address Description EraseBlock Parameters Name Address Description 11. Return values for Table Read Table Number Return Value ProtectBlock Parameters Name Address DescriptionEraseAll Parameters Name Address Description 10. Table Read Parameters Name Address Description Srom Table 12. Checksum Parameters Name Address Description ClockingChecksum Function Clock Block Diagram Bit 40 Gain Clock Architecture DescriptionIosc Trim Iosctr 0x34 R/W Bit 41 Reserved CPU/USB Clock Config Cpuclkcr 0x30 R/WLposc Trim Lposctr 0x36 R/W Bit 76 Reserved Bit 5 No Buzz OSC Control 0 OSCCR0 0x1E0 R/W = Tcapclk USB Osclock Clock Configuration Osclckcr 0x39 R/WTimer Clock Config Tmrclkcr 0x31 R/W Bit 72 Reserved Cou nte r Terru pt Ntro ller Document 38-08035 Rev. *K Interval Timer Clock ItmrclkTimer Capture Clock Tcapclk Clock IO Config Clkiocr 0x32 R/W CPU Clock During Sleep Mode Reset Reset Watchdog Timer Reswdt 0xE3 W Sleep ModePower on Reset Watchdog Timer Reset Wake up Sequence Sleep Sequence Wake Up Timing Low Power in Sleep Mode Bit 20 VM20 LVD Trip Point V Min Point V Typ Point V Max Low Voltage Detect ControlLow Voltage Control Register Lvdcr 0x1E3 R/W Bit 76 Reserved Bit 54 PORLEV10 ECO Ecotr 0x1EB R/W Voltage Monitor Comparators Register Vltcmp 0x1E4 RBit 72 Reserved Bit 1 LVD ECO Trim Register P0 Data Register P0DATA0x00 R/W General Purpose IO Gpio PortsPort Data Registers P3 Data Register P3DATA 0x03 R/W P1 Data Register P1DATA 0x01 R/WP2 Data Register P2DATA 0x02 R/W Gpio Port Configuration P0.1/CLKOUT Configuration P01CR 0x06 R/W P0.0/CLKIN Configuration P00CR 0x05 R/W P0.5/TIO0 P0.6/TIO1 Configuration P05CR-P06CR 0x0A-0x0B R/W P0.2/INT0-P0.4/INT2 Configuration P02CR-P04CR 0x07-0x09 R/W 12. P1.2 Configuration P12CR 0x0F R/W P0.7 Configuration P07CR 0x0C R/W10. P1.0/D+ Configuration P10CR 0x0D R/W 11. P1.1/D- Configuration P11CR 0x0E R/W 16. P2 Configuration P2CR 0x15 R/W 13. P1.3 Configuration P13CR 0x10 R/W14. P1.4-P1.6 Configuration P14CR-P16CR 0x11-0x13 R/W 15. P1.7 Configuration P17CR 0x14 R/W SPI Data Register Spidata 0x3C R/W 17. P3 Configuration P3CR 0x16 R/WSerial Peripheral Interface SPI SPI Data Register SPI Configure Register Sclk Ssel DAT a SPI Interface PinsSPI Mode Timing vs. LSB First, Cpol and Cpha Registers Timer RegistersFree Running Timer Low order Byte Frtmrl 0x20 R/W Free Running Timer High-order Byte Frtmrh 0x21 R/W Timer Capture 1 Falling TIO1F 0x25 R/W Timer Capture 0 Rising TIO0R 0x22 R/WTimer Capture 1 Rising TIO1R 0x23 R/W Timer Capture 0 Falling TIO0F 0x24 R/W 10. Programmable Interval Reload High Pirh 0x29 R/W Programmable Interval Timer High Pitmrh 0x27 RBit 74 Reserved Programmable Interval Reload Low Pirl 0x28 R/W Bit 20 Reserved Timer Capture11. Timer Configuration Tmrcr 0x2A R/W 13. Capture Interrupt Status Tcapints 0x2C R/W 12. Capture Interrupt Enable Tcapinte 0x2B R/W Timer Functional Sequence Diagram Bit Free Running Counter Loading Timing Diagram Architectural Description Interrupt Controller PCH PC158 is cleared to zero Interrupt ProcessingInterrupt Trigger Conditions Interrupt Latency Interrupt Clear 2 INTCLR2 0xDC R/W Interrupt RegistersInterrupt Clear 0 INTCLR0 0xDA R/W Interrupt Clear 1 INTCLR1 0xDB R/W Bit 60 Reserved Interrupt Mask 2 INTMSK2 0xDF R/W Bit 7 Enable Software Interrupt EnswintInterrupt Mask 3 INTMSK3 0xDE R/W Interrupt Mask 1 INTMSK1 0xE1 R/W Interrupt Vector Clear Register Intvc 0xE2 R/W Interrupt Mask 0 INTMSK0 0xE0 R/W Vreg Control Register Vregcr 0x73 R/W Regulator OutputVreg Control USB Serial Interface Engine SIE USB Transceiver ConfigurationUSB Transceiver Configure Register Usbxcr 0x74 R/W USB/PS2 Transceiver USB Device Address Usbcr 0x40 R/W USB DeviceUSB Device Address Endpoint 0, 1, and 2 Count Bit 30 Mode Endpoint 0 ModeEndpoint 0 Mode EP0MODE 0x44 R/W Endpoint 0 Data EP0DATA 0x50-0x57 R/W Endpoint 1 and 2 ModeEndpoint 1 and 2 Mode EP1MODE EP2MODE 0x45, 0x46 R/W Bit 7 Stall Endpoint 2 Data EP2DATA 0x60-0x67 R/W USB Mode TablesMode Column Encoding Column SETUP, IN, and OUT Columns Details of Mode for Differing Traffic Conditions Count Fifo Register Summary Addr Name Default Tmrcr Intvc Voltage vs CPU Frequency Characteristics Voltage Vs CPU Frequency Characteristics 3V Regulator DC CharacteristicsAbsolute Maximum Ratings Detect Cpuclk AC CharacteristicsGeneral Purpose IO Interface Parameter Description Conditions Min Typical Max Unit Clock SPI Timing Non-USB Mode Driver CharacteristicsUSB Data Timing Clock Timing Gpio Timing Diagram Differential Data Lines SCK CPOL=0 SCK CPOL=0 SCK CPOL=1 Package Handling Ordering Information Pin 300-Mil Molded DIP P1 Package Diagrams Pin 300-Mil Molded DIP P3 Pin 300-Mil Soic S13 Pin QFN Package Document History Removed Gpio port 4 configuration details Added block diagrams and timing diagramsUpdated part numbers in the header Removed 638xx die diagram and die form pad assignment CMCC/PYRS VGT/AESA USB Sales, Solutions, and Legal InformationWorldwide Sales and Design Support Products PSoC Solutions

Figure 28-1. Clock Timing

Figure 28-2. GPIO Timing Diagram

Figure 28-3. USB Data Signal Timing

Differential Data Lines

Figure 28-4. Receiver Jitter Tolerance

CY7C638xx, CY7C63310 specifications