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Cypress CY7C63310 Details of Mode for Differing Traffic Conditions, SETUP, IN, and OUT Columns

Models: CY7C638xx CY7C63310

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CY7C63310, CY7C638xx

22.3 SETUP, IN, and OUT Columns

Depending on the mode specified in the 'Encoding' column, the 'SETUP', 'IN', and 'OUT' columns contain the SIE's responses when the endpoint receives SETUP, IN, and OUT tokens, respectively.

A 'Check' in the Out column means that upon receiving an OUT token the SIE checks to see whether the OUT is of zero length and has a Data Toggle (Data1/0) of 1. If these conditions are true, the SIE responds with an ACK. If any of the these conditions is not met, the SIE responds with a STALL or Ignore.

A 'TX Count' entry in the IN column means that the SIE transmits the number of bytes specified in the Byte Count Bit [3:0] of the Endpoint Count Register (Table 21-2) in response to any IN token.

23. Details of Mode for Differing Traffic Conditions

Control Endpoint

SIE

Bus Event

SIE

EP0 Mode Register

EP0 Count Register

EP0

Interrupt

Comments

Mode

Token

Count

Dval

D0/1

Response

S

I

O

A

MODE

DTOG

DVAL

COUNT

FIFO

DISABLED

0000

x

x

x

x

Ignore All

STALL_IN_OUT

0011

SETUP

>10

x

x

junk

Ignore

0011

SETUP

<=10

invalid

x

junk

Ignore

0011

SETUP

<=10

valid

x

ACK

1

1

0001

update

1

update

data

Yes

ACK SETUP

0011

IN

x

x

x

STALL

Stall IN

0011

OUT

>10

x

x

Ignore

0011

OUT

<=10

invalid

x

Ignore

0011

OUT

<=10

valid

x

STALL

Stall OUT

NAK_IN_OUT

0001

SETUP

>10

x

x

junk

Ignore

0001

SETUP

<=10

invalid

x

junk

Ignore

0001

SETUP

<=10

valid

x

ACK

1

1

0001

update

1

update

data

Yes

ACK SETUP

0001

IN

x

x

x

NAK

NAK IN

0001

OUT

>10

x

x

Ignore

0001

OUT

<=10

invalid

x

Ignore

0001

OUT

<=10

valid

x

NAK

NAK OUT

ACK_IN_STATUS_OUT

1111

SETUP

>10

x

x

junk

Ignore

1111

SETUP

<=10

invalid

x

junk

Ignore

1111

SETUP

<=10

valid

x

ACK

1

1

0001

update

1

update

data

Yes

ACK SETUP

1111

IN

x

x

x

TX

Host Not ACK'd

1111

IN

x

x

x

TX

1

1

0001

Yes

Host ACK'd

1111

OUT

>10

x

x

Ignore

1111

OUT

<=10

invalid

x

Ignore

1111

OUT

<=10, <>2

valid

x

STALL

0011

Yes

Bad Status

1111

OUT

2

valid

0

STALL

0011

Yes

Bad Status

1111

OUT

2

valid

1

ACK

1

1

0010

1

1

2

Yes

Good Status

STATUS_OUT

0010

SETUP

>10

x

x

junk

Ignore

0010

SETUP

<=10

invalid

x

junk

Ignore

0010

SETUP

<=10

valid

x

ACK

1

1

0001

update

1

update

data

Yes

ACK SETUP

0010

IN

x

x

x

STALL

0011

Yes

Stall IN

0010

OUT

>10

x

x

Ignore

0010

OUT

<=10

invalid

x

Ignore

Document 38-08035 Rev. *K

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Cypress CY7C63310, CY7C638xx manual Details of Mode for Differing Traffic Conditions, SETUP, IN, and OUT Columns

CY7C638xx, CY7C63310 specifications

The Cypress CY7C63310 and CY7C638xx series are advanced USB microcontrollers designed for various applications requiring reliable performance and flexibility. These chips are notable for their integration of several key technologies, enabling developers to create innovative electronic designs effortlessly.

The CY7C63310 is a part of the Cypress USB microcontroller family that boasts a fully integrated 8051-compatible microprocessor core. This architecture allows for efficient execution of high-level programming languages like C, enhancing code development efforts. The microcontroller supports USB 2.0 full-speed operation, allowing for high data transfer rates of up to 12 Mbps, essential for applications involving data communication.

One of the standout features of the CY7C63310 is its programmable GPIO (General-Purpose Input/Output) pins, which provide developers with the versatility to configure these pins as inputs, outputs, or alternate functions. This flexibility is particularly advantageous in applications where custom interfaces are essential, such as human-machine interfaces, sensor control, and USB peripherals.

Moreover, the CY7C638xx series presents an even broader array of features. These devices typically support various memory configurations, enabling designers to select from different on-chip RAM and flash memory options. This variety empowers projects requiring a mix of program and data storage capabilities, all while ensuring that performance remains optimal.

Both the CY7C63310 and CY7C638xx series leverage Cypress's EZ-USB technology, which simplifies the process of USB interface implementation. The EZ-USB architecture minimizes the effort associated with USB protocol complexity, allowing developers to focus on the core functionality of their applications.

These microcontrollers also incorporate features such as low-power operation, making them ideal for battery-operated devices. With various power management modes, designers can optimize energy consumption according to the specific needs of their applications.

In terms of connectivity, these chips support multiple interface standards, including SPI, I2C, and UART. These capabilities ensure that developers can easily interface with other components and systems, enhancing the overall utility of the microcontroller.

In summary, the Cypress CY7C63310 and CY7C638xx microcontrollers stand out for their robust features, including integrated USB functionality, flexible GPIO options, and support for various communication protocols. These attributes make them suitable for a wide range of applications, from consumer electronics to industrial automation, making them an excellent choice for developers seeking reliable and adaptable microcontroller solutions.

Contents

Cypress Semiconductor Corporation 198 Champion Court FeaturesApplications San Jose, CA Document 38-08035 Rev. *K Revised December 08 Logic Block Diagram Gpio Introduction Conventions Pinouts Die Pad Summary Pad Number Pad Name Microns Gpio Port 1 bit 1/USB D- 1 If this pin is used as a Pin DescriptionGpio Port 1 bit 0/USB D+ 1 If this pin is used as a Supply CPU ArchitectureNo connect Ground CPU Registers Flags Register Addressing Modes 10. Destination Direct Opcode Operand Source Direct Opcode OperandSource Indexed Opcode Operand Destination Indexed 14. Destination Direct Source Direct Opcode Operand 12. Destination Direct Source Immediate Opcode Operand13. Destination Indexed Source Immediate Opcode Operand 15. Source Indirect Post Increment Opcode Operand Instruction Set Summary Instruction Set Summary Sorted Numerically by Opcode Order2 POR/LVD INT0 Memory OrganizationFlash Program Memory Organization EP0 EP1 EP2 Srom Data Memory OrganizationFlash Stack begins here and grows upward Srom Return Codes Description Srom Function DescriptionsSrom Function Parameters Variable Name Sram Address ReadBlock Parameters Name Address Description EraseBlock Parameters Name Address Description Protection Modes Settings Description MarketingWriteBlock Parameters Name Address Description Block Block n 10. Table Read Parameters Name Address Description ProtectBlock Parameters Name Address DescriptionEraseAll Parameters Name Address Description 11. Return values for Table Read Table Number Return Value Srom Table 12. Checksum Parameters Name Address Description ClockingChecksum Function Clock Block Diagram Bit 40 Gain Clock Architecture DescriptionIosc Trim Iosctr 0x34 R/W Bit 41 Reserved CPU/USB Clock Config Cpuclkcr 0x30 R/WLposc Trim Lposctr 0x36 R/W OSC Control 0 OSCCR0 0x1E0 R/W Bit 76 Reserved Bit 5 No Buzz Bit 72 Reserved USB Osclock Clock Configuration Osclckcr 0x39 R/WTimer Clock Config Tmrclkcr 0x31 R/W = Tcapclk Cou nte r Terru pt Ntro ller Document 38-08035 Rev. *K Interval Timer Clock ItmrclkTimer Capture Clock Tcapclk CPU Clock During Sleep Mode Clock IO Config Clkiocr 0x32 R/W Reset Watchdog Timer Reset Sleep ModePower on Reset Reset Watchdog Timer Reswdt 0xE3 W Sleep Sequence Wake up Sequence Low Power in Sleep Mode Wake Up Timing Bit 76 Reserved Bit 54 PORLEV10 Low Voltage Detect ControlLow Voltage Control Register Lvdcr 0x1E3 R/W Bit 20 VM20 LVD Trip Point V Min Point V Typ Point V Max ECO Trim Register Voltage Monitor Comparators Register Vltcmp 0x1E4 RBit 72 Reserved Bit 1 LVD ECO Ecotr 0x1EB R/W P0 Data Register P0DATA0x00 R/W General Purpose IO Gpio PortsPort Data Registers P3 Data Register P3DATA 0x03 R/W P1 Data Register P1DATA 0x01 R/WP2 Data Register P2DATA 0x02 R/W Gpio Port Configuration P0.0/CLKIN Configuration P00CR 0x05 R/W P0.1/CLKOUT Configuration P01CR 0x06 R/W P0.2/INT0-P0.4/INT2 Configuration P02CR-P04CR 0x07-0x09 R/W P0.5/TIO0 P0.6/TIO1 Configuration P05CR-P06CR 0x0A-0x0B R/W 11. P1.1/D- Configuration P11CR 0x0E R/W P0.7 Configuration P07CR 0x0C R/W10. P1.0/D+ Configuration P10CR 0x0D R/W 12. P1.2 Configuration P12CR 0x0F R/W 15. P1.7 Configuration P17CR 0x14 R/W 13. P1.3 Configuration P13CR 0x10 R/W14. P1.4-P1.6 Configuration P14CR-P16CR 0x11-0x13 R/W 16. P2 Configuration P2CR 0x15 R/W SPI Data Register 17. P3 Configuration P3CR 0x16 R/WSerial Peripheral Interface SPI SPI Data Register Spidata 0x3C R/W SPI Configure Register Sclk Ssel DAT a SPI Interface PinsSPI Mode Timing vs. LSB First, Cpol and Cpha Free Running Timer High-order Byte Frtmrh 0x21 R/W Timer RegistersFree Running Timer Low order Byte Frtmrl 0x20 R/W Registers Timer Capture 0 Falling TIO0F 0x24 R/W Timer Capture 0 Rising TIO0R 0x22 R/WTimer Capture 1 Rising TIO1R 0x23 R/W Timer Capture 1 Falling TIO1F 0x25 R/W Programmable Interval Reload Low Pirl 0x28 R/W Programmable Interval Timer High Pitmrh 0x27 RBit 74 Reserved 10. Programmable Interval Reload High Pirh 0x29 R/W Bit 20 Reserved Timer Capture11. Timer Configuration Tmrcr 0x2A R/W 12. Capture Interrupt Enable Tcapinte 0x2B R/W 13. Capture Interrupt Status Tcapints 0x2C R/W Timer Functional Sequence Diagram Bit Free Running Counter Loading Timing Diagram Interrupt Controller Architectural Description Interrupt Latency Interrupt ProcessingInterrupt Trigger Conditions PCH PC158 is cleared to zero Interrupt Clear 1 INTCLR1 0xDB R/W Interrupt RegistersInterrupt Clear 0 INTCLR0 0xDA R/W Interrupt Clear 2 INTCLR2 0xDC R/W Bit 60 Reserved Interrupt Mask 2 INTMSK2 0xDF R/W Bit 7 Enable Software Interrupt EnswintInterrupt Mask 3 INTMSK3 0xDE R/W Interrupt Mask 1 INTMSK1 0xE1 R/W Interrupt Mask 0 INTMSK0 0xE0 R/W Interrupt Vector Clear Register Intvc 0xE2 R/W Vreg Control Register Vregcr 0x73 R/W Regulator OutputVreg Control USB/PS2 Transceiver USB Transceiver ConfigurationUSB Transceiver Configure Register Usbxcr 0x74 R/W USB Serial Interface Engine SIE Endpoint 0, 1, and 2 Count USB DeviceUSB Device Address USB Device Address Usbcr 0x40 R/W Bit 30 Mode Endpoint 0 ModeEndpoint 0 Mode EP0MODE 0x44 R/W Bit 7 Stall Endpoint 1 and 2 ModeEndpoint 1 and 2 Mode EP1MODE EP2MODE 0x45, 0x46 R/W Endpoint 0 Data EP0DATA 0x50-0x57 R/W Encoding Column USB Mode TablesMode Column Endpoint 2 Data EP2DATA 0x60-0x67 R/W Details of Mode for Differing Traffic Conditions SETUP, IN, and OUT Columns Count Fifo Addr Name Default Register Summary Tmrcr Intvc Voltage Vs CPU Frequency Characteristics Voltage vs CPU Frequency Characteristics Detect DC CharacteristicsAbsolute Maximum Ratings 3V Regulator Parameter Description Conditions Min Typical Max Unit Clock AC CharacteristicsGeneral Purpose IO Interface Cpuclk SPI Timing Non-USB Mode Driver CharacteristicsUSB Data Timing Gpio Timing Diagram Clock Timing Differential Data Lines SCK CPOL=0 SCK CPOL=0 SCK CPOL=1 Ordering Information Package Handling Package Diagrams Pin 300-Mil Molded DIP P1 Pin 300-Mil Molded DIP P3 Pin 300-Mil Soic S13 Pin QFN Package Document History Removed 638xx die diagram and die form pad assignment Added block diagrams and timing diagramsUpdated part numbers in the header Removed Gpio port 4 configuration details VGT/AESA CMCC/PYRS USB Sales, Solutions, and Legal InformationWorldwide Sales and Design Support Products PSoC Solutions