EM78P156N

OTP ROM

• RF can be cleared by instruction but cannot be set.

• IOCF is the interrupt mask register.

• Note that the result of reading RF is the "logic AND" of RF and IOCF.

8. R10 ~ R3F

• All of these are 8-bit general-purpose registers.

4.2 Special Purpose Registers1. A (Accumulator)

• Internal data transfer, or instruction operand holding

• It cannot be addressed.

2. CONT (Control Register)

7

 

6

 

5

4

3

2

1

 

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

-

 

/INT

 

TS

TE

PAB

PSR2

PSR1

PSR0

 

• Bit 0 (PSR0) ~ Bit 2 (PSR2) TCC/WDT prescaler bits.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PSR2

 

PSR1

PSR0

 

TCC Rate

 

 

WDT Rate

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

0

0

 

1:2

 

 

1:1

 

 

 

 

0

0

1

 

1:4

 

 

1:2

 

 

 

 

0

1

0

 

1:8

 

 

1:4

 

 

 

 

0

1

1

 

1:16

 

 

1:8

 

 

 

 

1

0

0

 

1:32

 

 

1:16

 

 

 

 

1

0

1

 

1:64

 

 

1:32

 

 

 

 

1

1

0

 

1:128

 

 

1:64

 

 

 

 

1

1

1

 

1:256

 

 

1:128

 

 

 

•Bit 3 (PAB) Prescaler assignment bit.

0:TCC

1:WDT

•Bit 4 (TE) TCC signal edge

0:increment if the transition from low to high takes place on TCC pin

1:increment if the transition from high to low takes place on TCC pin

•Bit 5 (TS) TCC signal source

0:internal instruction cycle clock

1:transition on TCC pin

•Bit 6 (/INT) Interrupt enable flag

0:masked by DISI or hardware interrupt

1:enabled by ENI/RETI instructions

•Bit 7 Not used.

This specification is subject to change without prior notice. 12

07.29.2004 (V1.2)