ELANsat Tech EM78P156N Address Trap Detect

EM78P156N

OTP ROM

	Vdd
	/Rese	Tvr
		Tvr
	Internal	Tvd
	Internal
	POR	Tpor
	Power	Tpor
	Power
	on

Symbol	Parameter	Condition	Min.	Typ.	Max.	Unit

Tpor	Power on reset time	Vdd = 5V, -40℃to 85℃	10.5	16.8	22	ms

Tvd	Vdd Voltage drop time	Vdd = 5V, -40℃to 85℃	-	-	1*	us

Tvr	Vdd Voltage rise time	Vdd = 5V, -40℃to 85℃	-	-	1**	us

*Tvd is the period of Vdd voltage less than POR voltage.

**Tvr is the period of Vdd voltage higher than 5.5 volts.

Address Trap Detect

An address trap detect is one of the fail-safe function that detects CPU malfunction caused by noise or the like. If the CPU attempts to fetch an instruction from a part of RAM, an internal recovery circuit will auto started. Until CPU got the correct function, it will execute the following program.

This specification is subject to change without prior notice. 57

07.29.2004 (V1.2)

Contents

8-BIT MICRO-CONTROLLER Version EM78P156N Specification Revision History Version Content Application Note 1. GENERAL DESCRIPTION 2. FEATURES Page 3. PIN ASSIGNMENTS Table 2 EM78P156NAS Pin Description Table 3 EM78P156NKM Pin Description 4. FUNCTION DESCRIPTION 3.R2 (Program Counter) & Stack On-chipProgram Memory Fig. 3 Program Counter Organization Address R PAGE registers IOC PAGE registers CONT IOC5 4. R3 (Status Register) Bit 0 (C) • Bit (DC) (Z) 4.2 Special Purpose Registers 1. A (Accumulator) 2. CONT (Control Register) Bit 3 (PAB) Bit 4 (TE) 3. IOC5 ~ IOC6 (I/O Port Control Register) 4. IOCA (Prescaler Counter Register) 5. IOCB (Pull-downControl Register) Bit 0 (/PD0) Bit 1 (/PD1) Bit 5 (OD5) Bit 6 (OD6) Bit 7 (OD7) 7. IOCD (Pull-highControl Register) Bit 0 (/PH0) 4.3 TCC/WDT & Prescaler 4.4 I/O Ports Fig. 6 The Circuit of I/O Port and I/O Control Register for Port Fig. 7(a) The Circuit of I/O Port and I/O Control Register for P60 (/INT) Fig. 7(b) The Circuit of I/O Port and I/O Control Register for P61~P67 Fig. 7(c) Block Diagram of I/O Port 6 with Input Change Interrupt/Wake-up Table 4 Usage of Port 6 Input Change Wake-up/InterruptFunction (I) (II) Fig. 8 The Circuit of I/O Port with R-option(P50,P51) 4.5RESET and Wake-up 1.RESET Page Table 5 The Summary of the Initialized Values for Registers 2.The Status of RST, T, and P of STATUS Register Table 6 The Values of RST, T and P after RESET Fig. 9 Block Diagram of Controller Reset 4.6 Interrupt 4.7Oscillator 1.Oscillator Modes Table 8 Oscillator Modes Defined by OSC and HLP Table 9 The Summary of Maximum Operating Speeds 2. Crystal Oscillator/Ceramic Resonators (XTAL) Fig. 11 Circuit for External Clock Input Fig. 12 Circuit for Crystal/Resonator Table 10 Capacitor Selection Guide for Crystal Oscillator or Ceramic Resonator 3. External RC Oscillator Mode 4.8CODE Option Register 1. Code Option Register (Word 0) •Bit 12 、11 、10 、9:Not used. Reserved Bit 8 (CLKS) Bit 7(ENWDTB) Bit 6: 4.9Power On Considerations 4.10 External Power On Reset Circuit 4.11 Residue-VoltageProtection Fig. 15 Circuit 1 for the Residue Voltage Protection 4.12 Instruction Set Page Page 4.13 Timing Diagrams AC Test Input/Output Waveform RESET Timing (CLK="0") TCC Input Timing (CLKS="0") 5.ABSOLUTE MAXIMUNM RATINGS EM78P156N 6.ELECTRICAL CHARACTERISTICS 6.2 AC Electrical Characteristic Vih/Vil (Input pins with schmitt inverter) Vth (Input thershold voltage) of I/O pins Voh/Ioh (5V) Vol/Iol (5V) Fig. 21 Port5, Port6 Vol vs. Iol, VDD Vol/Iol (3V) Fig. 22 Port5, Port6 Vol vs. Iol, VDD WDT Time out Cext = 100pF, Typical RC Frequency vs. VDD Typical ICC1 and ICC2 vs. Temperature Maximum ICC1 and ICC2 vs. Temperature Typical ICC3 and ICC4 vs. Temperature Maximum ICC3 and ICC4 vs. Temperature Typical ISB1 and ISB2 vs. Temperature Maximum ISB1 and ISB2 vs. Temperature Page EM78P156N-JHXT EM78P156N-JLXT EM78P156N-GHXT EM78P156N-GLXT APPENDIX Package Information 18-LeadPlastic Small Outline (SOP) — 300 mil 20-LeadPlastic Small Outline (SSOP) — 209 mil Quality Assurance And Reliability Address Trap Detect