EM78P156N
OTP ROM
• CONT register is both readable and writable.
3. IOC5 ~ IOC6 (I/O Port Control Register)• "1" put the relative I/O pin into high impedance, while "0" defines the relative I/O pin as output.
• Only the lower 4 bits of IOC5 can be defined.
• IOC5 and IOC6 registers are both readable and writable.
4. IOCA (Prescaler Counter Register)• IOCA register is readable.
• The value of IOCA is equal to the contents of Prescaler counter.
• Down counter.
5. IOCB7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
|
|
|
|
|
|
|
/PD7 | /PD6 | /PD5 | /PD4 | - | /PD2 | /PD1 | /PD0 |
• Bit 0 (/PD0) Control bit is used to enable the |
|
| |||||
0: Enable internal |
|
|
|
|
| ||
1: Disable internal |
|
|
|
|
| ||
• Bit 1 (/PD1) Control bit is used to enable the |
|
| |||||
• Bit 2 (/PD2) Control bit is used to enable the |
|
| |||||
• Bit 3 | Not used. |
|
|
|
|
|
|
• Bit 4 (/PD4) Control bit is used to enable the
• Bit 5 (/PD5) Control bit is used to enable the
• Bit 6 (/PD6) Control bit is used to enable the
• Bit 7 (/PD7) Control bit is used to enable the
• IOCB Register is both readable and writable.
6. IOCC
| 7 | 6 | 5 |
| 4 | 3 | 2 | 1 |
| 0 |
|
|
|
|
|
|
|
|
|
|
|
| |
| OD7 | OD6 | OD5 |
| OD4 | OD3 | OD2 | OD1 |
| OD0 |
|
| • Bit 0 (OD0) Control bit is used to enable the |
|
|
|
| ||||||
| 0: Disable |
|
|
|
|
|
|
| |||
| 1: Enable |
|
|
|
|
|
|
| |||
| • Bit 1 (OD1) Control bit is used to enable the |
|
|
|
| ||||||
| • Bit 2 (OD2) Control bit is used to enable the |
|
|
|
| ||||||
| • Bit 3 (OD3) Control bit is used to enable the |
|
|
|
| ||||||
| • Bit 4 (OD4) Control bit is used to enable the |
|
|
|
| ||||||
|
|
|
|
|
|
| |||||
This specification is subject to change without prior notice. | 13 |
|
|
| 07.29.2004 (V1.2) |
|