ELANsat Tech EM78P156N Fig. 9 Block Diagram of Controller Reset, Table 6 The Values of RST, T and P after RESET

EM78P156N

OTP ROM

1.A power-on condition,

2.A high-low-high pulse on /RESET pin, and

3.Watchdog timer time-out.

The values of T and P, listed in Table 4 are used to check how the processor wakes up. Table 5 shows the events that may affect the status of T and P.

Table 6 The Values of RST, T and P after RESET

Reset Type	T	P
Power on	1	1
/RESET during Operating mode	*P	*P
/RESET wake-up during SLEEP mode	1	0
WDT during Operating mode	0	*P
WDT wake-up during SLEEP mode	0	0
Wake-Up on pin change during SLEEP mode	1	0

*P: Previous status before reset

Table 7 The Status of T and P Being Affected by Events.

Event			T	P
Power on			1	1
WDTC instruction			1	1
WDT time-out			0	*P
SLEP instruction			1	0
Wake-Up on pin change during SLEEP mode			1	0
*P: Previous value before reset
		VDD
		D	Q	CLK
Oscillator		CLK
		CLR
Power-on
Reset
Voltage
Detector
WDTE
WDT	WDT Timeout		Setup Time	RESET

/RESET

Fig. 9 Block Diagram of Controller Reset

This specification is subject to change without prior notice. 24 07.29.2004 (V1.2)