ELANsat Tech EM78P156N Fig. 7(b) The Circuit of I/O Port and I/O Control Register for P61~P67, Fig. 7(c) Block Diagram of I/O Port 6 with Input Change Interrupt/Wake-up

EM78P156N

OTP ROM

PCRD

			Q	P	D
				R
			_	CLK		PCWR
			Q	C
				L
P61~P67				P		IOD
PORT			Q		D
				R		PDWR
			_	CLK
			Q	C
				L
	0	M
	1	U
		X
						TIN
						PDRD
		D	P	Q
			R
		CLK		_
			C
				Q
			L

NOTE: Pull-high (down) and Open-drain are not shown in the figure.

Fig. 7(b) The Circuit of I/O Port and I/O Control Register for P61~P67

IOCE.1
D	P	Q
	R
CLK		_				Interrupt
	C
		Q
	L
			RE.1
						ENI Instruction
T10		D	P	Q
			R
T11		CLK		Q	P	D
					R
			C	_
			L	Q	CLK
				_

Q C

L

T17

DISI Instruction

Interrupt

(Wake-up from SLEEP)

/SLEP

Next Instruction

(Wake-up from SLEEP)

Fig. 7(c) Block Diagram of I/O Port 6 with Input Change Interrupt/Wake-up

This specification is subject to change without prior notice. 18 07.29.2004 (V1.2)