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ELANsat Tech EM78P156N 2.The Status of RST, T, and P of STATUS Register

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EM78P156N

OTP ROM

Address

Name

Reset Type

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

/RESET and WDT

P

P

P

P

P

P

P

P

Wake-Up from Pin Change

P

P

P

P

P

P

P

P

Bit Name

X

X

X

X

X

EXIF

ICIF

TCIF

0x0F

RF(ISR)

Power-On

U

U

U

U

U

0

0

0

/RESET and WDT

U

U

U

U

U

0

0

0

Wake-Up from Pin Change

U

U

U

U

U

P

P

P

Bit Name

-

-

-

-

-

-

-

-

0x0A

IOCA

Power-On

1

1

1

1

1

1

1

1

/RESET and WDT

1

1

1

1

1

1

1

1

Wake-Up from Pin Change

P

P

P

P

P

P

P

P

Bit Name

/PD7

/PD6

/PD5

/PD4

X

/PD2

/PD1

/PD0

0x0B

IOCB

Power-On

1

1

1

1

U

1

1

1

/RESET and WDT

1

1

1

1

U

1

1

1

Wake-Up from Pin Change

P

P

P

P

U

P

P

P

Bit Name

OD7

OD6

OD5

OD4

OD3

OD2

OD1

OD0

0x0C

IOCC

Power-On

0

0

0

0

0

0

0

0

/RESET and WDT

0

0

0

0

0

0

0

0

Wake-Up from Pin Change

P

P

P

P

P

P

P

P

Bit Name

/PH7

/PH6

/PH5

/PH4

/PH3

/PH2

/PH1

/PH0

0x0D

IOCD

Power-On

1

1

1

1

1

1

1

1

/RESET and WDT

1

1

1

1

1

1

1

1

Wake-Up from Pin Change

P

P

P

P

P

P

P

P

Bit Name

WDTE

EIS

X

ROC

X

X

X

X

0x0E

IOCE

Power-On

1

0

U

0

U

U

U

U

/RESET and WDT

1

0

U

0

U

U

U

U

Wake-Up from Pin Change

1

P

U

P

U

U

U

U

Bit Name

X

X

X

X

X

EXIE

ICIE

TCIE

0x0F

IOCF

Power-On

U

U

U

U

U

0

0

0

/RESET and WDT

U

U

U

U

U

0

0

0

Wake-Up from Pin Change

U

U

U

U

U

P

P

P

Bit Name

-

-

-

-

-

-

-

-

0x10~0x2F

R10~R2F

Power-On

U

U

U

U

U

U

U

U

/RESET and WDT

P

P

P

P

P

P

P

P

Wake-Up from Pin Change

P

P

P

P

P

P

P

P

**To jump address 0x08, or to execute the instruction which is next to the “SLEP” instruction. X: Not used. U: Unknown or don’t care. P: Previous value before reset. t: Check Table 4

2.The Status of RST, T, and P of STATUS Register

A RESET condition is initiated by the following events:

This specification is subject to change without prior notice. 23

07.29.2004 (V1.2)

Contents

8-BIT MICRO-CONTROLLER Version EM78P156N Specification Revision History Version Content Application Note 1. GENERAL DESCRIPTION 2. FEATURES Page 3. PIN ASSIGNMENTS Table 2 EM78P156NAS Pin Description Table 3 EM78P156NKM Pin Description 4. FUNCTION DESCRIPTION 3.R2 (Program Counter) & Stack On-chipProgram Memory Fig. 3 Program Counter Organization Address R PAGE registers IOC PAGE registers CONT IOC5 4. R3 (Status Register) Bit 0 (C) • Bit (DC) (Z) 4.2 Special Purpose Registers 1. A (Accumulator) 2. CONT (Control Register) Bit 3 (PAB) Bit 4 (TE) 3. IOC5 ~ IOC6 (I/O Port Control Register) 4. IOCA (Prescaler Counter Register) 5. IOCB (Pull-downControl Register) Bit 0 (/PD0) Bit 1 (/PD1) Bit 5 (OD5) Bit 6 (OD6) Bit 7 (OD7) 7. IOCD (Pull-highControl Register) Bit 0 (/PH0) 4.3 TCC/WDT & Prescaler 4.4 I/O Ports Fig. 6 The Circuit of I/O Port and I/O Control Register for Port Fig. 7(a) The Circuit of I/O Port and I/O Control Register for P60 (/INT) Fig. 7(b) The Circuit of I/O Port and I/O Control Register for P61~P67 Fig. 7(c) Block Diagram of I/O Port 6 with Input Change Interrupt/Wake-up Table 4 Usage of Port 6 Input Change Wake-up/InterruptFunction (I) (II) Fig. 8 The Circuit of I/O Port with R-option(P50,P51) 4.5RESET and Wake-up 1.RESET Page Table 5 The Summary of the Initialized Values for Registers 2.The Status of RST, T, and P of STATUS Register Table 6 The Values of RST, T and P after RESET Fig. 9 Block Diagram of Controller Reset 4.6 Interrupt 4.7Oscillator 1.Oscillator Modes Table 8 Oscillator Modes Defined by OSC and HLP Table 9 The Summary of Maximum Operating Speeds 2. Crystal Oscillator/Ceramic Resonators (XTAL) Fig. 11 Circuit for External Clock Input Fig. 12 Circuit for Crystal/Resonator Table 10 Capacitor Selection Guide for Crystal Oscillator or Ceramic Resonator 3. External RC Oscillator Mode 4.8CODE Option Register 1. Code Option Register (Word 0) •Bit 12 、11 、10 、9:Not used. Reserved Bit 8 (CLKS) Bit 7(ENWDTB) Bit 6: 4.9Power On Considerations 4.10 External Power On Reset Circuit 4.11 Residue-VoltageProtection Fig. 15 Circuit 1 for the Residue Voltage Protection 4.12 Instruction Set Page Page 4.13 Timing Diagrams AC Test Input/Output Waveform RESET Timing (CLK="0") TCC Input Timing (CLKS="0") 5.ABSOLUTE MAXIMUNM RATINGS EM78P156N 6.ELECTRICAL CHARACTERISTICS 6.2 AC Electrical Characteristic Vih/Vil (Input pins with schmitt inverter) Vth (Input thershold voltage) of I/O pins Voh/Ioh (5V) Vol/Iol (5V) Fig. 21 Port5, Port6 Vol vs. Iol, VDD Vol/Iol (3V) Fig. 22 Port5, Port6 Vol vs. Iol, VDD WDT Time out Cext = 100pF, Typical RC Frequency vs. VDD Typical ICC1 and ICC2 vs. Temperature Maximum ICC1 and ICC2 vs. Temperature Typical ICC3 and ICC4 vs. Temperature Maximum ICC3 and ICC4 vs. Temperature Typical ISB1 and ISB2 vs. Temperature Maximum ISB1 and ISB2 vs. Temperature Page EM78P156N-JHXT EM78P156N-JLXT EM78P156N-GHXT EM78P156N-GLXT APPENDIX Package Information 18-LeadPlastic Small Outline (SOP) — 300 mil 20-LeadPlastic Small Outline (SSOP) — 209 mil Quality Assurance And Reliability Address Trap Detect