EM78P156N

OTP ROM

CLK=Fosc/4 is used if CLK bit is "1". If TCC signal source comes from external clock input, TCC is increased by 1 at every falling edge or rising edge of TCC pin.

•The watchdog timer is a free running on-chip RC oscillator. The WDT will keep on running even when the oscillator driver has been turned off (i.e. in sleep mode). During normal operation or sleep mode, a WDT time-out (if enabled) will cause the device to reset. The WDT can be enabled or disabled any time during normal mode by software programming. Refer to WDTE bit of IOCE register. Without prescaler, the WDT time-out period is approximately 18 ms1 (default).

CLK(=Fosc/2 or Fosc/4)

 

 

 

Data Bus

 

 

 

 

 

 

0

M

1

 

 

 

TCC

M

SYNC

TCC (R1)

 

Pin

U

U

 

2 cycles

 

 

 

1

X

X

 

 

 

 

 

TE

 

0

 

 

 

 

 

TCC overflow interrupt

 

 

TS

PAB

 

 

 

 

 

0

M

 

 

 

 

 

8-bit Counter

M

IOCA

WDT

U

 

 

U

 

X

 

 

 

1

 

 

X

 

 

 

 

 

WTE

PAB

 

 

PAB

Initial

(in IOCE)

8-to-1 MUX

 

 

 

 

 

 

PSR0~PSR2

value

 

 

 

 

 

 

 

0

1

 

 

 

 

 

MUX

PAB

 

 

 

 

 

 

 

 

WDT time-out

 

 

Fig. 5 Block Diagram of TCC and WDT4.4 I/O Ports

The I/O registers, both Port 5 and Port 6, are bi-directional tri-state I/O ports. Port 6 can be pulled high internally by software. In addition, Port 6 can also have open-drain output by software. Input status change interrupt (or wake-up) function on Port 6. P50 ~ P52 and P60 ~ P63 pins can be pulled down by software. Each I/O pin can be defined as "input" or "output" pin by the I/O control register (IOC5 ~ IOC6). P50~P51 are the R-option pins enabled by setting the ROC bit in the IOCE register to 1. When the

1<Note>: Vdd = 5V, set up time period = 16.8ms ± 30% Vdd = 3V, set up time period = 18ms ± 30%

This specification is subject to change without prior notice. 16

07.29.2004 (V1.2)