Cavium Processor Complex: Memory
10009109-01 ATCA-9305 User’s Manual 3-9
MEMORY
The processor complex supports DDR2 Synchronous DRAM (SDRAM) and Reduced Latency
DRAM (RLDRAM) memory devices.
DDR2 SDRAM
The ATCA-9305 supports up to 16 gigabytes of 144-bit wide DDR2 SDRAM per processor
complex. The SDRAM interface clock speed frequency is 400 MHz. The four low-profile,
dual-inline memory modules (buffered DIMM) are installed in 240-pin very low profile (VLP)
sockets to reduce board density and routing constraints. A 2 KB EEPROM on the DIMM pro-
vides the serial presence detection (SPD). On-card SDRAM occupies physical addresses
from 0,0000,0000,000016 to 0,0003,FFFF,FFFF16.
Each processor memory bus is operating in 144-bit mode. Error-correcting Code (ECC) is
performed on the memory bus so that the CN5860 detects all double-bit errors, multi-bit
errors within a nibble, and corrects all single-bit errors.
RLDRAM
Each CN5860 supports 256 MB Common I/O (CIO) RLDRAM operating up to 400 MHz
(depends on the processor speed). The Micron RLDRAM II is organized as 32Mx18x8 internal
banks. The DDR I/O interface transfers two data words per clock cycle. Output data is refer-
enced to the free-running output data clock. Read and write accesses to the RLDRAM are
burst-oriented. RLDRAM is accessed by using Cavium-specific instructions which operate on
MIPS Coprocessor 2.
I2C EEPROM
Each Cavium processor complex has one user EEPROM device for parameter storage located
on the I2C bus, address 0xA8. The I2C bus for each processor is completely independent
from the other CN5860 processor and MPC8548 processor I2C buses. The Atmel two-wire
serial EEPROM on each CN5860 processor I2C interface consists of the Serial Clock (SCL)
input and the Serial Data (SDA) bidirectional lines.
stdin serial Sets the standard source for console input
Valid options: serial, pci
stdout serial Sets the standard destination for console output
Valid options: serial, pci
Variable:
Default
Value: Description: (continued)