Cavium ProcessorComplex: Memory

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

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Variable:

 

Value:

 

Description: (continued)

 

 

stdin

 

serial

 

Sets the standard source for console input

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Valid options: serial, pci

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

stdout

 

serial

 

Sets the standard destination for console output

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Valid options: serial, pci

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MEMORY

The processor complex supports DDR2 Synchronous DRAM (SDRAM) and Reduced Latency DRAM (RLDRAM) memory devices.

DDR2 SDRAM

The ATCA-9305 supports up to 16 gigabytes of 144-bit wide DDR2 SDRAM per processor complex. The SDRAM interface clock speed frequency is 400 MHz. The four low-profile, dual-inline memory modules (buffered DIMM) are installed in 240-pin very low profile (VLP) sockets to reduce board density and routing constraints. A 2 KB EEPROM on the DIMM pro- vides the serial presence detection (SPD). On-card SDRAM occupies physical addresses from 0,0000,0000,000016 to 0,0003,FFFF,FFFF16.

Each processor memory bus is operating in 144-bit mode. Error-correcting Code (ECC) is performed on the memory bus so that the CN5860 detects all double-bit errors, multi-bit errors within a nibble, and corrects all single-bit errors.

RLDRAM

Each CN5860 supports 256 MB Common I/O (CIO) RLDRAM operating up to 400 MHz (depends on the processor speed). The Micron RLDRAM II is organized as 32Mx18x8 internal banks. The DDR I/O interface transfers two data words per clock cycle. Output data is refer- enced to the free-running output data clock. Read and write accesses to the RLDRAM are burst-oriented. RLDRAM is accessed by using Cavium-specific instructions which operate on MIPS Coprocessor 2.

I2C EEPROM

Each Cavium processor complex has one user EEPROM device for parameter storage located on the I2C bus, address 0xA8. The I2C bus for each processor is completely independent from the other CN5860 processor and MPC8548 processor I2C buses. The Atmel two-wire serial EEPROM on each CN5860 processor I2C interface consists of the Serial Clock (SCL) input and the Serial Data (SDA) bidirectional lines.

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ATCA-9305 User’s Manual

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Emerson ATCA-9305 user manual Cavium Processor Complex Memory, DDR2 Sdram, Rldram, I2C Eeprom
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ATCA-9305 specifications

The Emerson ATCA-9305 is a high-performance AdvancedTCA (ATCA) chassis designed to meet the demanding requirements of telecommunications and IT infrastructure. With a focus on scalability, reliability, and flexibility, this equipment is ideal for service providers and enterprises looking to deploy robust applications in a variety of environments.

One of the main features of the ATCA-9305 is its support for high-density blade configurations. The chassis can accommodate up to 14 ATCA blades, enabling the deployment of powerful processing units, communication modules, and storage solutions. This level of density not only maximizes space but also minimizes power consumption, which is crucial for reducing operational costs in large-scale deployments.

The ATCA-9305 is built with a focus on advanced thermal management and redundancy. It employs a sophisticated cooling architecture that ensures optimal airflow across the chassis, preventing overheating during operation. Additionally, the chassis features hot-swappable fans and power supplies, which means that components can be replaced without interrupting the overall system performance. This capability enhances uptime and reliability, which is essential for mission-critical applications.

Another notable characteristic of the ATCA-9305 is its support for various interconnect technologies. The chassis provides robust backplane options that facilitate high-bandwidth communication between blades. It supports Ethernet, PCI Express, and Serial RapidIO, allowing for seamless integration with existing infrastructure and future technologies. This flexibility enables organizations to adapt to changing market demands and technological advancements.

Security features are also a prominent aspect of the ATCA-9305. The chassis incorporates hardware-based security modules that enhance data integrity and protect sensitive information. This is particularly important for service providers who must adhere to strict regulatory compliance standards.

In terms of management and monitoring, the ATCA-9305 is equipped with advanced management capabilities. It supports AdvancedTCA Management Interface (IPMI) and other monitoring protocols, allowing administrators to easily oversee the health and performance of the entire system. This level of visibility aids in proactive maintenance and troubleshooting, effectively reducing downtime.

In conclusion, the Emerson ATCA-9305 is a powerful and versatile chassis that stands out due to its high-density configuration, advanced thermal management, diverse interconnect technology support, robust security features, and comprehensive management capabilities. Its design is tailored for the evolving needs of telecommunications and data center environments, making it a valuable asset for any organization looking to enhance its infrastructure.
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