Cavium Processor Complex: PCI
10009109-01 ATCA-9305 User’s Manual 3-3
The CN5860 processor is designed such that another PCI device can initialize its memory
interface, copy code over PCI into its local memory space, and then write a boot release reg-
ister.
CN5860 Boot Over PCI
The PCI bus is configured to run at 66 MHz in 64-bit conventional PCI mode. On power-up,
the CN5860 processor’s 16 internal cores are held in reset. The MPC8548 management pro-
cessor performs the following steps:
1Initialize the CN5860 RAM.
2Copy the CN5860 U-boot to the CN5860 RAM.
3Copy boot code to the reset vector to jump to the U-boot code in RAM.
4Release the CN5860 processor cores from reset.
5Receive return codes from the CN5860 that indi cate any boot or POST errors and take the
appropriate action.
The management processor (MPC8548) monitor implements a utilit y to load non-volatile
memory redundant U-boot images for the CN5860 processors. The utility tags each copy as
primary or secondary.