Emerson ATCA-9305 user manual PLD Version, PLL Reset Configuration, Hardware Configuration

Management Processor CPLD: MPC8548 PLD Register

PLD Version

This read-only register tracks PLD revisions.

Register 5-3:PLD Version (0x08)

Bits:	Function:	Description:
7	0	This is hard coded in the PLD and changes with every released code
		change. Version starts at 0016.
6	0
5	0
4	0
3	0
2	0
1	0
0	0

PLL Reset Configuration

Write to this register to reconfigure the SYSCLK to CCB clock ratio and the CCB to CORE clock ratio using valid values from the MPC8548E PowerQUICC™ III Integrated Processor Family Reference Manual. The changes take affect when the processor is reset (for example, the software hard reset command or watchdog timer expires). Default values are restored when the board is power-cycled, front panel reset is pressed, or receives a PCI reset that was not the result of the MPC8548 software initiating a PCI RSTOUT command.

Register 5-4:PLL Reset Configuration (0x0C)

Bits:	Function:	Description:
7	reserved
6	CCCB2	CCB2 to CORE clock ratio
5	CCCB1	CCB1 to CORE clock ratio
4	CCCB0	CCB0 to CORE clock ratio
3	CCBSYS3	SYSCLOCK3 to CCB clock ratio
2	CCBSYS2	SYSCLOCK2 to CCB clock ratio
1	CCBSYS1	SYSCLOCK1 to CCB clock ratio
0	CCBSYS0	SYSCLOCK0 to CCB clock ratio

Hardware Configuration 0

The read-only HCR0 allows the MPC8548 monitor software to easily determine specific hardware configurations, such as the processor clock and MPC8548 DDR memory.

10009109-01 ATCA-9305 User’s Manual

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