Management Processor CPLD: MPC8548 PLD Register

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Bits:

 

Function:

 

Description: (continued)

 

 

 

 

 

 

3

 

 

 

 

 

P2GPIO3OE

 

Processor 2 GPIO3 Output Enable

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

This is an input from the Cavium to reset the MIP3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2

 

 

 

 

 

P1GPIO5OE

 

Processor 1 GPIO5 Output Enable (enabled is the default)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Output enable is set for the TIC timer output to the Cavium

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

 

 

 

 

 

P1GPIO4OE

 

Processor 1 GPIO4 Output Enable

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

This is an input from the Cavium to reset the MIP2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

 

 

 

 

 

P1GPIO3OE

 

Processor 1 GPIO3 Output Enable

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

This is an input from the Cavium to reset the MIP1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Cavium GPIO Data Out

This register is the data that will be driven on the GPIO line when the Output enable is set.

Register 5-25:Cavium GPIO Data Out (0x84)

Bits:

Function:

Description:

7

reserved

 

6

reserved

 

5

reserved

 

4

P2GPIO4

Set the value of the Cavium 2 GPIO bit 4

 

 

 

3

P2GPIO3

Set the value of the Cavium 2 GPIO bit 3

 

 

 

2

reserved

 

1

P1GPIO4

Set the value of the Cavium 1 GPIO bit 4

 

 

 

0

P1GPIO3

Set the value of the Cavium 1 GPIO bit 3

 

 

 

Cavium GPIO Data In

This register reads the value on the GPIO lines connected to each Cavium.

Register 5-26:Cavium GPIO Data In (0x88)

Bits:

Function:

Description:

7

reserved

 

6

reserved

 

5

reserved

 

4

P2GPIO4

Read the value of the Cavium 2 GPIO bit 4

 

 

 

3

P2GPIO3

Read the value of the Cavium 2 GPIO bit 3

 

 

 

2

reserved

 

1

P1GPIO4

Read the value of the Cavium 1 GPIO bit 4

 

 

 

0

P1GPIO3

Read the value of the Cavium 1 GPIO bit 3

 

 

 

10009109-01

ATCA-9305 User’s Manual

5-13

Page 78 Page 80
Page 79
Image 79
Emerson ATCA-9305 user manual Cavium Gpio Data Out
Page 78 Page 80

ATCA-9305 specifications

The Emerson ATCA-9305 is a high-performance AdvancedTCA (ATCA) chassis designed to meet the demanding requirements of telecommunications and IT infrastructure. With a focus on scalability, reliability, and flexibility, this equipment is ideal for service providers and enterprises looking to deploy robust applications in a variety of environments.

One of the main features of the ATCA-9305 is its support for high-density blade configurations. The chassis can accommodate up to 14 ATCA blades, enabling the deployment of powerful processing units, communication modules, and storage solutions. This level of density not only maximizes space but also minimizes power consumption, which is crucial for reducing operational costs in large-scale deployments.

The ATCA-9305 is built with a focus on advanced thermal management and redundancy. It employs a sophisticated cooling architecture that ensures optimal airflow across the chassis, preventing overheating during operation. Additionally, the chassis features hot-swappable fans and power supplies, which means that components can be replaced without interrupting the overall system performance. This capability enhances uptime and reliability, which is essential for mission-critical applications.

Another notable characteristic of the ATCA-9305 is its support for various interconnect technologies. The chassis provides robust backplane options that facilitate high-bandwidth communication between blades. It supports Ethernet, PCI Express, and Serial RapidIO, allowing for seamless integration with existing infrastructure and future technologies. This flexibility enables organizations to adapt to changing market demands and technological advancements.

Security features are also a prominent aspect of the ATCA-9305. The chassis incorporates hardware-based security modules that enhance data integrity and protect sensitive information. This is particularly important for service providers who must adhere to strict regulatory compliance standards.

In terms of management and monitoring, the ATCA-9305 is equipped with advanced management capabilities. It supports AdvancedTCA Management Interface (IPMI) and other monitoring protocols, allowing administrators to easily oversee the health and performance of the entire system. This level of visibility aids in proactive maintenance and troubleshooting, effectively reducing downtime.

In conclusion, the Emerson ATCA-9305 is a powerful and versatile chassis that stands out due to its high-density configuration, advanced thermal management, diverse interconnect technology support, robust security features, and comprehensive management capabilities. Its design is tailored for the evolving needs of telecommunications and data center environments, making it a valuable asset for any organization looking to enhance its infrastructure.
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