Management Processor CPLD: MPC8548 PLD Register

Table 5-2:Low Frequency Timer Settings

Frequency:

Set Register:

Comments:

0

Off

Never interrupts

 

 

 

1 Hz

19999 (0x4E1F)

These frequencies require the use of both registers

 

 

 

10 Hz

1999 (0x7CF)

 

 

 

 

100 Hz

199 (0xC7)

 

 

 

 

1 KHz

19 (0x13)

 

 

 

 

10 KHz

1

This equals two 50 μs time units (default)

 

 

 

RTM GPIO State

This read-only register reads the current state of the GPIO pins.

Register 5-18:RTM GPIO State (0x60)

Bits:

Function:

Description:

7

RTM_GPIO 7

 

 

 

 

6

RTM_GPIO 6

 

 

 

 

5

RTM_GPIO 5

 

 

 

 

4

RTM_GPIO 4

 

 

 

 

3

RTM_GPIO 3

 

 

 

 

2

RTM_GPIO 2

 

 

 

 

1

RTM_GPIO 1

 

 

 

 

0

RTM_GPIO 0

 

 

 

 

RTM GPIO Control

This register sets the state of the GPIO pins. These signals are implemented as open collec- tor signals.

Register 5-19:RTM GPIO Control (0x64)

Bits:

Function:

Description:

7

RTM_GPIO 7

0 Causes the corresponding bit to be driven to 0

 

 

1 Tristates the signal; this will either be read by the RTM as a 1

6

RTM_GPIO 6

 

 

or can be driven by the RTM to any value

5

RTM_GPIO 5

 

 

 

 

4

RTM_GPIO 4

 

 

 

 

3

RTM_GPIO 3

 

 

 

 

2

RTM_GPIO 2

 

 

 

 

1

RTM_GPIO 1

 

 

 

 

0

RTM_GPIO 0

 

 

 

 

RTM Status

The RTM identification (ID) is determined by factory installed configuration resistors.

5-10

ATCA-9305 User’s Manual

10009109-01

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Emerson ATCA-9305 user manual RTM Gpio State, RTM Gpio Control, RTM Status, Frequency Set Register Comments, Rtmgpio

ATCA-9305 specifications

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